Electronics > FPGA

timed state machines VHDL

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sahko123:
having done some probing with a scope i figured out that the actual issue isnt metastabality but simply in how i read the pin in question  (a comparator output). at some points in time it will simply be out of phase and will miss an entire count of the comparator. shown below is a graph of the what happens when the comparator goes in and out of sync with the comparator.

sahko123:
and a more telling example

dmills:

--- Quote from: tggzzz on March 17, 2023, 08:54:05 am ---Plus that also notes the important point I made earlier, ... "A classic error is to have an asynchronous signal a the input to two flip flops, so the one can go one way and the second the other way."

--- End quote ---
Note that this implies that bringing anything more then a single signal across unrelated clock domains is HARD unless you know that the multi bit signal is something like a counter with a defined sequence, in which case gray code gets it done. The issue being that the various bits on the bus may or may not be transferred correctly if they change too close to a sampling edge.
I have seen an attempt to use gray code to bring an arbitrary data bus across clock domains, it worked "poorly".

Almost all the FPGA vendors have a FIFO based block that does this by essentially using hardware that is guaranteed to have the correct timing between the various strobes to ensure that the transfer is atomic. It is not so far as I am aware possible to build this logic in generic fabric and have a guarantee that it will always work.

In the xilinx case this magic is built into the dual port block ram based fifo core.

tggzzz:

--- Quote from: dmills on March 17, 2023, 01:40:36 pm ---
--- Quote from: tggzzz on March 17, 2023, 08:54:05 am ---Plus that also notes the important point I made earlier, ... "A classic error is to have an asynchronous signal a the input to two flip flops, so the one can go one way and the second the other way."

--- End quote ---
Note that this implies that bringing anything more then a single signal across unrelated clock domains is HARD unless you know that the multi bit signal is something like a counter with a defined sequence, in which case gray code gets it done. The issue being that the various bits on the bus may or may not be transferred correctly if they change too close to a sampling edge.
I have seen an attempt to use gray code to bring an arbitrary data bus across clock domains, it worked "poorly".

Almost all the FPGA vendors have a FIFO based block that does this by essentially using hardware that is guaranteed to have the correct timing between the various strobes to ensure that the transfer is atomic. It is not so far as I am aware possible to build this logic in generic fabric and have a guarantee that it will always work.

In the xilinx case this magic is built into the dual port block ram based fifo core.

--- End quote ---

Intuition makes me suspect that a multibit signal with sufficient added redundancy could traverse a clock domain reliability. But then having a separate single "databus steady" signal is almost certainly better in most cases!

However, instantiation of a predefined block is the way to go, as with many other functional blocks in FPGAs.

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