Electronics > FPGA

tRAS definition for DDR memory

(1/2) > >>

promach:
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This seems contradicts with Micron document.

AndyC_772:
The Micron data sheet is for a DDR3L device, but the System Verilog spec is talking about a feature added to DDR4.

Are you sure you're comparing like with like?

SiliconWizard:
Yes this isn't the same type of memory. But I can't see any mention of "tRAS" in figure 3 of the page you mention anyway?

asmi:
9 * tREFI is the upper bound of tRAS, basically it's the absolute maximum time a row can be held open. 9 * REFI is because of this:

--- Quote ---To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate.
--- End quote ---

promach:
@asmi  but Micron document defines tRAS as the timing between ACTIVATE command and PRECHARGE command.

@SiliconWizard  look at the Micron document on the left of the picture

Navigation

[0] Message Index

[#] Next page