Trion FPGA PLL instantiation in Verilog

[davorin]

Good afternoon

To use a PLL on a Trion FPGA you have to use the Interface Designer to set input/output names and clock multiplier/divider....and then assign the dedicated PLL input to a GPIO pin...so far so good.

In the pt_demo example I see that the PLL signals have to be used in the interface definition fot he Verilog top module....but seems my PLL clock is ignored therefore leading to a design where it throws an error that only VCC and GND nets are generated...

Code: [Select]

module test_lcd
(
input pll_clk,
output wire [0:7] R,
output wire [0:7] G,
output wire [0:7] B,
output wire LCD_CLK,
output wire LCD_HSYNC,
output wire LCD_VSYNC,
output wire LCD_DEN,
output wire LCD_PWM
);

Someone knows what the trick is in Efinity IDE to correctly use a PLL?
Don't know why they don't use the same approach as Xilinx and Quartus to generate a Verilog file to be included in your design instead.


thanks in advance

[mon2]

See if this helps:

https://www.digikey.ca/en/videos/e/efinix-inc/efinix-development-tool-tutorial-simple-pll-creation-in-interface-designer

If not, can share the contact for a FAE in the USA via a PM.

[davorin]

Found my stupid mistake ;-)

During migration from Anlogic to Efinix I deleted the pll instantination which outputted a reset signal to the timing module....so it used 0 as a constant driver ;-)

Still have to get used to the Efinity IDE.....