EEVblog Electronics Community Forum
Electronics => FPGA => Topic started by: ChewChew on August 29, 2022, 03:01:04 pm
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I’m very new to WinCUPL and PLDs. My only previous experience with logic was over 20 years ago at uni using Xilinx FPGA so forgive me if I’m missing something obvious.
I’m attempting to implement two independent frequency dividers on a 16V8. I see from the datasheet that all the D flip flops on the chip share the same clock so I tried implementing a simple D type using the logic array. This seems to work in simulation, but when I feedback nQ to D to make a toggle I get both compilation and WinSim errors.
A few days of struggling and Googling hasn’t helped. Much of the WinCUPL stuff I can find is pretty basic.
Has anyone got any hints or tips they can share?
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The global clock makes GALs rather limited for some applications - what sort of frequencies and divde rations are you trying to get ?
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Sorry, I should have included this - 1MHz and 7MHz. Both /2
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Sorry, I should have included this - 1MHz and 7MHz. Both /2
If the sources are asynchronous then you can't easily do it in one device. You probably could do 0.5 and 3.5 from a common 7M source though.
I suppose you may be able to implement an independent DFF in async logic for one of them, but an external HC74 may be a better solution.
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This is what I’m trying to recreate.
[attach=1]
It's a HD PC FDD modified to work in an Amiga. The trick required to get it working with HD floppies is to send a 32 bit sequence (0101….) clocked by drive select to identify a HD disk has been inserted and to halve the motor driver frequency when reading the disk. Hence the need for two independent dividers.
I’ve got this working using a couple of 74 series ICs on a breadboard and now looking to migrate to a neat small package.
Owners of these FDDs advise the device is a 16V8. I have a few spare, so I took on the challenge......