Understanding a circuit

[joniengr081]

Hi, I a circuit and I need to understand how it works. There is a schematic in attachment. There are four differential comparators in the IC but I don't understand how the output signals PG-1V0, PG-ALL, and PG-POR-B are driven by the input signals.

[tggzzz]

Firstly tell us the purpose of the circuit. Then describe what you think the circuit ought to be doing. [1] Finally, re-draw the schematic using the standard conventions for op-amp and comparator circuits. I believe there are four independent comparators in the LM339, so draw them as such.

Writing down that explanation might be enough for you to understand how it works.

[1] I'm not going to waste my time double-guessing information that you already have.
https://entertaininghacks.wordpress.com/library-2/good-questions-pique-our-interest-and-dont-waste-our-time-2/

[pcprogrammer]

And also tell us how this is FPGA releated?

To me this topic belongs in the beginners section. You can use the move topic button on the bottom of the page to move it to that section.

[joniengr081]

Yes this is an IC in the schematic of a ZYNQ development board ZedBoard and my guess is that this is a sequencer but I am not getting what is the sequence of the outputs on different channels.

[SiliconWizard]

Yeah there is no feedback as far as I can tell (not hugely fond of those generic block symbols for opamps), so this is just a bunch of comparators.

[tggzzz]

Yeah there is no feedback as far as I can tell (not hugely fond of those generic block symbols for opamps), so this is just a bunch of comparators.

The way it is drawn helps obfuscate what the design does and how it works. I suggested the OP redraw it, but they seem to know better. Oh well.

[luudee]

The circuit is a "Power Good" controller.

It monitors input voltages and asserts PG-1V0 when VCC1V0 has met  it's minimal threshold,
then it asserts PG-ALL when other Voltages rails are in their normal operation range, and finally,
it will assert (release) PS-POR-B (Processor Power On Reset).

I did not do the math to verify if it will actually work, only glanced over it ...

Cheers,
luudee

[joniengr081]

Hi luudee, I also think that this is a power good circuit for ZYNQ FPGA.

First PG-1V0 then PG-ALL and then PS-POR-B (Processor Power On Reset) but I am not able to understand their relations or connections to the applied input.

[joniengr081]

IN1+ => 1 V
IN1- => (43/(43+100))*3.0 = 0.90 V

IN2+ => ??
IN2- => (43/(43+100))*3.0 = 0.90 V 

IN3+ => PG-ALL
IN3- => VREF3V0

IN4+ => ??
IN4- => (24/(24+100))*3.0 = 0.58 V

[EPAIII]

Your circuit is very easy to understand if you read the LM339 datasheet.

https://www.ti.com/lit/ds/symlink/lm239.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1671568309756&ref_url=https%253A%252F%252Fwww.mouser.mx%252F

The LM339 is four, independent Voltage comparators in a single package. That's all it is. So, using the one labeled #1 in your schematic, here is how that one works.

The #1 comparator has inputs on pins 4 and 5 and the output on pin 2. The outputs of the four comparators have an "open collector" configuration which means that there is an internal transistor with it's emitter connected to Gnd and the emitter goes to the output pin with no internal connections. This means that, in order to function, that transistor must have an external load resistor. That is R260, 100K in your schematic. That resistor tries to pull the output pin, #2 high and the comparator's internal circuitry can pull it low. This allows the IC to operate with one power supply while the circuit connected to the output can have another. For instance, the IC may have a 12 Volt supply while the load circuit may operate on 24 VDC.

The inputs for the 1 comparator should have Voltages between Gnd and Vcc (0 - 5 V in your schematic). Pin 4 is the inverting input and pin 5 is the non-inverting input. If the Voltage on pin 5 is higher than that on pin 4 then the open collector transistor in the IC is not turned on and the output is raised high by R260. And if the Voltage on pin 5 is lower than that on pin 4 then the open collector transistor in the IC is turned on and the output is driven low by that transistor.

Output 1, pin 2 has two additional components attached to it. They do not have much effect on the output logic. They are apparently there to protect the load (Zener diode, D23) and perhaps to filter the output or shape the rising and falling edges (capacitor, C36). I would need to see the circuit this output is attached to in order to explain them better than this.

The inputs to pins 4 and 5 are:

Pin 4 comes from a Voltage divider made of R258 and R259. They are connected between VREFV0 and Ground. The schematic does not tell us what VREFV0 is so the best I can say is the Voltage on pin 4 (Vpin4) will be:

Vpin4 = VREFV0 x 43,000/(43,000 + 100,000)

It appears that VREFV0 is a fixed reference Voltage created in some other part of the circuit. So Vpin4 should also be a fixed Voltage. But I could be wrong in this.

Pin 5 is connected to VCC1V0.

So Out1 on pin 2 will be:

High or VCC5V0 if VCC1V0 > Vpin4
and
low or Ground if VCC1V0 < Vpin4

That explains how the first comparator operates using the information available in your schematic. The other three comparators operate in a like manner but take their reference and checked Voltages from different places. It is not difficult so I leave it to the reader to work out the logic tables for them.

Comparator 2 uses the same reference (from R258 and R259) as comparator 1. This does not mean that they have any relationship other than that common reference. Nothing flows between the two input pins: 4 and 6. Both just have the same reference Voltage.

On the output side, Outputs 2 and 4 are connected and they share the same load resistor, R261. Since the two open collector transistors share the same load resistor, either one can pull the output line low. This is called a wired OR circuit. If Out2 OR Out4 is low, then the output line is LOW. Both must be high for the output line to be high. This output line has the same output protection/modification as Out1: D24 and C368.

Pin 7, In 2+ has a more complicated input circuit (R263, R265, and R269 all precision resistors). Each of these resistors comes from different Voltages from other parts of the circuit so I can not explain their interaction. Only that it is the combined Voltage that goes to pin 7 that matters. The line PG-DDR, which is connected to pin 7, goes to or comes from somewhere else. Again, without information about that connection, nothing further can be said.

[luudee]

Hi luudee, I also think that this is a power good circuit for ZYNQ FPGA.

First PG-1V0 then PG-ALL and then PS-POR-B (Processor Power On Reset) but I am not able to understand their relations or connections to the applied input.

I would not use it for FPGA.

For FPGA, your DC/DC power supplies (in sequence) will generate a last "Power Good" signal - use that ...

luudee

[SiliconWizard]

Hi luudee, I also think that this is a power good circuit for ZYNQ FPGA.

First PG-1V0 then PG-ALL and then PS-POR-B (Processor Power On Reset) but I am not able to understand their relations or connections to the applied input.

I would not use it for FPGA.

For FPGA, your DC/DC power supplies (in sequence) will generate a last "Power Good" signal - use that ...

luudee

Uh yeah, as long as they do. Which, they do not necessarily. Not all buck converters have a PG output, and having to limit yourself to those that do will just make your life much harder especially in times of shortage.

But otherwise there are also ICs that are dedicated power sequencers, some including a few buck converters in one chip. Nice to know they exist, but sometimes you need to use alternatives.