Understanding SDI video data format

[Wiljan]

1) What may be the expected current consumption of the 2.5V  VCCA supply pins of EP4CE6E22? They should be just PLL supply pins. (trying to determine if a 150mA SOT23 LDO would do).

I can't find any mA  for the VCCA but I would expect that 150mA would be enough, mayby you can messure it on your own board (remember to add 2 PLL's and run them eg @ 100Mhz and 200Mhz)

Here https://www.waveshare.com/wiki/OpenEP4CE6-C_User_Manual they use the AMS1117-2.5 so if your 150mA are not good enough you can swap the LDO later on

2) How to interface the damn CLC001 (datasheet) cable driver to the FPGA? Seems like I need to "waste" a whole IO bank due to 2.5V VCCIO requirement.

Datasheet mentions CLC001 accepts both LVPECL and LVDS voltage levels. The FPGA can do both LVPECL and LVDS.

Datasheet specifies the input common mode range of CLC001 to be 50mV to 3.25V. Does that mean I can DC couple it to the FPGA? The Cyclone IV handbook (Volume 3 Table 1-20 page 14) specifies that LVDS has a Vos = 1.25V. That means choosing LVDS would enable direct DC coupling to the CLC001, with just a single 100ohm termination resistor on the CLC001 side of the line.  No other resistors required. Is that correct?

I agree it look like one 100ohm resistor can do the rick and you can leave the I/O Bank as  you have it
The CLC001 needs 3V3  Vdd    you might like to have 1 Bank running 3V3 for unknown purpose

You can test it on you board just send the 27Hhz to LVDS pins and hook up the CLC001 and look at the scope

[Yansi]

Thank you for confirming my thoughts.

I meant that only the bank with LVDS used needs to be supplied with 2V5 and I have selected bank 6 to do so. One with the least amount of pins and also right side of the die, where the true LVDS drivers are.  All other banks will have 3V3 VCCIO.

Yesterday I did nothing with the board, some work troubles and related stuff.  But I'd like to continue today.

I have found another interesting issue to think about:

How to connect the clock line of ADV7391?

With the TVP5150, I can route it simply to any of the CLK pins nearby.  But I can't connect it together to the ADV7391. Imagine the following:  I'd like to use the FPGA to generate video signal, such as a test pattern generator. The ADV7391 can do much higher resolutions than SD, so I would need a completely different (and independent) clock from the FPGA. Where should I route the ADV7391 CLK pin then?

Likely any of the generic IOs, huh? But in case I would like to run in sync with the clock from TVP5150, how do I route the clock through the FPGA? The CLK signal delay within the FPGA may then cause incorrect timing on the output side. Not sure how to solve this one. Could you please give advice?


//EDIT: I have also doubly solved my oscilloscope issue: I have ordered a new one: Rigol DS1104Z. Its also Chinese one, but hey, shall be way better than the Hantek DSO5202B I got here for the last so many years.  At least the Rigol should have a proper intensity grading display and 4 channels.
I also got at home an old Agilent 3062A, that desperately needed some encoder change-out I have already done yesterday evening. A pretty boring oscilloscope nonetheless with absolutely horrible LCD screen, but at least I have a working backup for some basic poking.

[Wiljan]

How to connect the clock line of ADV7391?

With the TVP5150, I can route it simply to any of the CLK pins nearby.  But I can't connect it together to the ADV7391. Imagine the following:  I'd like to use the FPGA to generate video signal, such as a test pattern generator. The ADV7391 can do much higher resolutions than SD, so I would need a completely different (and independent) clock from the FPGA. Where should I route the ADV7391 CLK pin then?

Likely any of the generic IOs, huh? But in case I would like to run in sync with the clock from TVP5150, how do I route the clock through the FPGA? The CLK signal delay within the FPGA may then cause incorrect timing on the output side. Not sure how to solve this one. Could you please give advice?

I think:
The ADV7391 clk needs to come for the FPGA and not directly from the TVP5150 so you can program it via PLL or switch to internal global clocklines

Since we still talk about relative low freq I think you can use whatever outpin to drive clk on the ADV7391 to have the data "aligned" with the clk just send them trough registers clocked with the same clk and if should be in phase on the output eg if you do a test signal

On the ADV7391 eval board  ADV739x_EvalBrd_RevB.pdf http://media.digikey.com/PDF/Data%20Sheets/Analog%20Devices%20PDFs/ADV739x_EvalBrd_RevB.pdf
you can see the have 27Mhz (SD) and 74,25Mhz (HD) to pin 55 and 56 (global clk lines)  on spartan 3 and the they have clkout on pin 74 output on pin which goes to clk pin on ADV7391

And data clk into pin 53 and 125 via jumper as if it came from the TVP5150 to global clk lines

If they are routed to PLL or not I don't know since the HDL source for that board seems to be only available if you buy it (or I just can find it)

page 146  https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf
55 IO_L32P_4/GCLK0
56 O_L32N_4/GCLK1
74 IO_L01N_3/VRP_3

I have ordered a new one: Rigol DS1104Z

I love when new equipment are ordred  sure you will happy for 4 channels 

[Yansi]

Or I can put a jumper in there, to select clock in between a random IO pin and to connect together with TVP5150 clock. That could I think be possible too.
 

I have ordered a new one: Rigol DS1104Z

I love when new equipment are ordred  sure you will happy for 4 channels 

If I just could find out about Siglent SDS1204CFL, I would have probably bought that one. I like the dedicated knobs.
What I have found interesting, is that my freshly repaired Agilent DS3062A scope is in fact made by Siglent, not Agilent. 

[Wiljan]

Or I can put a jumper in there, to select clock in between a random IO pin and to connect together with TVP5150 clock. That could I think be possible too.
 

I have ordered a new one: Rigol DS1104Z

I love when new equipment are ordred  sure you will happy for 4 channels 

If I just could find out about Siglent SDS1204CFL, I would have probably bought that one. I like the dedicated knobs.
What I have found interesting, is that my freshly repaired Agilent DS3062A scope is in fact made by Siglent, not Agilent. 

Yes to Jumper, but maybe as solder connection to avoid RF issues in the connections over time

I have a 4ch Agillient DSOX2014A now Keysight and way back HP,  great scope with a lot of options 

[Yansi]

Agree, will use a solder jumper there.

That kind of oscilloscope is way out of my budget, unfortunately. If I would have that much to spend, I'd be likely looking for a new spectrum analyzer, to replace the aging one I have.

A little bit of an update: Board space is filling up nicely Been doing research around how to connect the configuration pins, FLASH and JTAG connector. I would like to also add some kind of a user button/switch. Already having 4 user LEDS, but being able to add something like a 4-way DIL switch, would be handy.

Also there is a 36pin header ready for future expansion and stuff.  The MCU is supposed to make a USB to UART/SPI/I2C bridge. All these three buses will be connected to the FPGA of course.

I will publish the schematic and layout for review later, currently still working on both on the fly.

[Yansi]

Little update with the board, see below. TVP5150 fully connected, IO expansion header also connected.

Today, unfortunately, I will again have to do some work related stuff, so will not probably do much progress either. At least I will figure out what to slap in the free space on the right. I don't like wasted space on PCBs 

The 34 pin (there was a mistake, 36pin is NOT a standard IDC size, I had to shave 2 off*) header provides 20 IOs directly to the FPGA - should be plenty for some  future toying. Provides also a lot of grounds, 3V3 supply voltage, the system I2C bus and a global /RESET signal for all peripherals.

[Wiljan]

When I bought that scope like 7 years ago there was a huge offer / campaign  at that time like almost half price, I newer regret it I bought it, special when there is a very good thread her in the forum with a good tricks 

Nice progress with your board 

YES have some dip SW and a few push buttons so you can easy trigger or select some part in the FPGA, very handy when debugging in real time. You have the IDC pins but say if you still have some spare I/O, you could use them as test connections (small rings) next to the edge to attach scope probes and also make an easy and steady connection for scope ground.

[Yansi]

I plan to put testpoints all over the board, ideally on all signals. Not sure how many spare IOs the FPGA will have, but I guess some will be left on the top side of PCB, estimating one whole bank free (~15 IOs?)

Of course it would make sense to break out as much pins as possible. Will put some thought into it.  .. .after I deal with the work related stuff now. 

[BrianHG]

If you can run that 1 IO bank at 1.8v, add this 1 chip which will use 12 IOs, even if you never populate it.

https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S70KS1281DPBHV020/2015-S70KS1281DPBHV020-ND/9955180

[Yansi]

Very interesting interface that memory has. Never seen one like this.  I hate BGA packages (not enough experience with them yet), but a 5x5 ball 1mm pitch looks as a nice beginner BGA chip, doesn't it? Almost looks like a challenge to try.  However it is quite on the expensive side, for just a DRAM.

The other board I plan to make will have a "classic" SDRAM with a 16bit wide IO.  Probably easier to start with, rather than the beast above with DDR and all sorts of hurdles? I smell way more complex interface than that of a classic cheap SDRAM.

Now I need just a board to start with simple video and even simpler VHDL stuff. Anyway thanks for an interesting tip.

[BrianHG]

Very interesting interface that memory has. Never seen one like this.  I hate BGA packages (not enough experience with them yet), but a 5x5 ball 1mm pitch looks as a nice beginner BGA chip, doesn't it? Almost looks like a challenge to try.  However it is quite on the expensive side, for just a DRAM.

The other board I plan to make will have a "classic" SDRAM with a 16bit wide IO.  Probably easier to start with, rather than the beast above with DDR and all sorts of hurdles? I smell way more complex interface than that of a classic cheap SDRAM.

Now I need just a board to start with simple video and even simpler VHDL stuff. Anyway thanks for an interesting tip.

It has a built in DRAM controller (this is why it is expensive).  All you need to do if feed an address and either write data, or wait for the read data ready flag and receive data.  It handles the refresh and sequence timing internally.  Logic wise, a simple state machine with a home made FPGA FIFO line buffer, and you will have enough speed for NTSC 4 field processing like XYZ 3D comb filtering dot crawl removal and noise removal, and/or 480i to 480p de-interlacing processing if your encoder/DAC supports 27MHz 1:1 through mode.  (Some NTSC encoders do support 480p as well)

Your FPGA already has enough in it to do 3 line XY filtering like median noise filter, sharpen & blur,  the ram brings this into 3D-Z processing.

A single 5x5 1mm BGA can be placed with just some solder on the pads, a blob of flux and hot air.
https://youtu.be/2eXMFIkdA0o

The ram chip may be cheaper from somewhere else other than Digikey.

[Yansi]

Well, I can try fit it there, but that's another likely whole day of fiddling to get the BGA on the board.  I'd rather leave fiddling with external RAM for next attempt.  Now I'd be glad if this board would work as it should as it is.

You know that I am no VHDL/FPGA expert,  don't you? My freaking blinkenlights project with UART transmitter doesn't qualify me for 3D-Z processing, at least not yet.  I'd be plenty happy if I could insert some dumb text into the video. 

And regarding Louis:

"How hot is your air gun?"
"I dunno. Whatever it needs to be to melt shit. If it's not hot enough to melt shit, turn it up!"

I need some BGA practice first.   

[Wiljan]

If you can run that 1 IO bank at 1.8v, add this 1 chip which will use 12 IOs, even if you never populate it.

https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S70KS1281DPBHV020/2015-S70KS1281DPBHV020-ND/9955180

Interesting device, never pay any attention to those but it removes all the refresh issues 

How fast is it?

If you have like 2 SD (or more) video inputs you could sure use it as framebuffer to make sync / zoom, freeze etc, but I suspect there would be limitation if eg you should use it for a 90 deg rotation of a video frame (this would normal require SRAM to not be limited to read / write a whole row in DRAM)?

[Yansi]

A question regarding the JTAG download cable connection:  Do the JTAG pins of Cyclone IV support 3V3 levels, or do they not? I am finding confusing and even contradicting information in the device handbook. 

Shall I power the JTAG interface from 3V3, or 2V5?

The Cyclone IV device handbook (page 211) tells me to power the JTAG interface from the VCCA (Analog! 2V5) supply. WTF! Is that a misprint or what?

And I have checked on the small FPGA kit I got and the JTAG cable is powered from 3V3.
Then I have checked the larger FPGA kit I have and the JTAG there is also powered 3V3.

Also I am not finding any information, that would prohibit me from applying 3V3 to the JTAG interface.  Table 1-1 the Absolute Max Ratings just generically states a maximum input voltage is 4.2V. Hence I think that applies even to JTAG pins.

Yes I have also noticed there are no clamping diodes on the JTAG pins, I have added a diode array on the PCB to solve that.

For device using VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 8–23. All I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 V. You must power up the VCC of the download cable with a 2.5-V supply from VCCA.

But WHYYYYYYYYYYYYY 

[Yansi]

Pcb is finaly done! Took a day more than I thought. But still, quite fast if I would sum all hours up. The layout is not the best, but 've at least tried.    (Still likely better than that cheap Chinese kit and wire nest).

Please find below some fancy 3D views and a schematic of the FPGA connections - if anyone would like to have a peek and confirm no obvious rookie mistakes have been made there.

My comments to the schematic:

VCCINT = 1.2V, VCCIO = 3V3 except one bank with LVDS (VCCIO = 2V5), VCCA = 2V5

MSEL(2:0) pins configured according to device handbook page 173, table 8-5 as "010" (POR Delay standard, 3V3 config). Log 1 is at VCCA (2V5).

JTAG cable powered from 3V3 VCCIO - I have copied what works for others. Pinout should match USB Blaster.  ESD protection and clamp diode array added to JTAG interface.

Please check the configuration FLASH is connected to the correct pins. I use the original recommended EPCS4 device (but sure I know it is a bog standard 25 series FLASH).

nCONFIG pin can be triggered by the onboard MCU via USB command (at least that is the plan - if wondering where the pin goes)

54MHz XO clock provided to the CLK1 net,  27MHz clock from TVP5150 provided to CLK7 net

[BrianHG]

Approximate ram speed:
100 megabytes per second with a burst length set to 16.  (Using 27Mhz X 6 in PLL X2 for DDR = 324 MTPS)
Add 50% for a burst length of 32.  Speed improves further as you increase burst up to 128.

For a 90 degree rotate (really advanced, even more so than 3D XYZ image filtering/processing), you do realize that NTSC&PAL are interlaced, without deinterlacing, you will have crap results, but if 240p is acceptable (old super-nintendo type resolution), then you are ok.  You also want 4 fields of memory for de-interlacing.  That's a good 16 megabytes for 422 16bit color PAL.  1 entire ram chip.

Also, with the memory bursts being sequential, and if you want to use a burst of 16, you will need 3 blocks of 16 line buffers inside the FPGA where you store a triple incoming video buffer where you rotate chunks of display in blocks of 16x16 pixels over an entire 16 lines of video.

This means that you would want (say for efficiency in allocation within CycloneIV M9K ram blocks):
720 pixels x 20 bit color x 16 lines x 4 buffers =
1024 x 18bits x 16lines x 4buffers = 1179648 bits of FPGA ram = 128 M9k CycloneIV ram blocks.
The smallest Cyclone IV has only 270kbits, or, 30 M9k blocks.

If you do some trickery to get the line buffers down to 16lines by 1 buffer, you still need 32 M9K blocks.
I would recommend using the EP4CE10 as it has almost double the M9K blocks of ram at 414kbit, or, 46 M9K blocks.

(No matter how you allocate ram in Quartus, it will always round up to 1 M9K block at a time, or if you go above 9 bits to 10 bits, this also may double your allocated memory as is will be considered an 18bit wide ram with the final 8 bits ignored.  The compiler may attempt some optimizations depending on memory depth and how it may divide into a single M9K block.)

(Except for 2 or 3 pins different, the 144pin QFP EP4CE6 and EP4CE10 a almost pin for pin compatible.  Make sure your PCB is already wired to accept either both FPGAs.  The larger 144pin EP4CE15 and largest EP4CE22 have a few IO swapped to VCCint and GNDint.  If you don't need those particular IOs, you should move them to the larger EP4CE15/22 and in Quartus, even if you placed the smaller FPGA, just set those IOs to unused inputs.  This way you can use any FPGA size if you ever need to.)

Don't forget to add a dummy TTL RS232 IO port for good measure.

That big hole under you FPGA, I assume you will be filling it with solder as the heat sink?
Also, here is another third party schematic as reference for the JTAG and AS (Active Serial port), and serial prom wiring for reference:
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/?action=dlattach;attach=871688
I don't see any protection diodes on the JTAG and it is being powered from the 2.5v regulator with 2.5v on the pullups.  The AS active serial port is using the 3.3v.

This board has been used extensively here:
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg2783910/#msg2783910
We know it works.

[Yansi]

I thought E4CE6 and EP4CE10 in E144 package are 100% compatible. So what pins are not? I did not see a difference in between them. Better ask and solve that now than later.   

The board I've made has a small MCU on it, that can act as a USB <> UART/SPI/I2C bridge. (Only later I have realized I could use it as an FPGA programmer, using the PS configuration mode (Passive Serial) - so just maybe on the next board).

Yes that hole below is to solder the exposed pad. I could try solder it using just paste and hot air, but I doubt I could center it on the pads while hot-airing it down or risk damaging an IC or two. I know this hack is ugly, but should lead to a working result.

[Wiljan]

Approximate ram speed:

Thank you for pointing out the RAM requirement for the video handling, very informative 

My question were a bit more on the PSRAM device itself what is the worst case speed in the device if reading / writing just 1 byte in random location (that was why I mention rotation since you have to swat the row / column)

Normal DRAM perform badly in "just" 1 byte since you have to read/write the whole and SRAM excellent so I guess the PSRAM will be slow as well, is that correct?

A few interesting links to video rotate I had in bookmark 
http://www8.cs.umu.se/education/examina/Rapporter/robertn.pdf
https://web.wpi.edu/Pubs/E-project/Available/E-project-012317-181821/unrestricted/slammqp_final.pdf
https://weekly-geekly.github.io/articles/325236/index.html

[Yansi]

Thanks for sharing the papers,  I am currently reading the first one and I find it pretty interesting!

//I almost am accepting as a challenge now to try implementing it. Great stuff!

//I've also found an interesting and very cheap video encoder by reading the paper: Philips SAA7120. Great!

//This looks it uses the same algorithm (I mean the rotozoomer), although I can't really orient myself well in the VHDL code from that project:
http://www.elektronika.kvalitne.cz/PLA/TFT_tests/TFT_tests_eng.html

[Wiljan]

//This looks it uses the same algorithm (I mean the rotozoomer), although I can't really orient myself well in the VHDL code from that project:
http://www.elektronika.kvalitne.cz/PLA/TFT_tests/TFT_tests_eng.html

More rotozoom https://www.fpga4fun.com/GraphicLCDpanel3.html

[Yansi]

Although it is a verilog, I can see it there.

Meanwhile the PCB is being manufactured, I could probably play with one of the FPGA kits I have, to at least get some practice in VHDL. So let's begin with some blinkenlights again 

[Yansi]

It is surprising how much can one forget, if not using a skill. I haven't touched VHDL for like what... maybe 4-5 years?

A simple blinkenlight LED display counter took me almost 2 hours to figure out. (The syntax and strict type policies are just an awful stuff!)



And sure even those 4-5 years back I wasn't any kind of expert. Hopefully I will now have more time and more useful ideas what to do with an FPGA, that will keep me learning further.

Now I have a week (or maybe two) to play with blinkenlights to gain some of the knowledge back, before the PCBs arrive.   

[Yansi]

After taking a bit of break from video and toying with VHDL at other projects, look what we finally got here!

A PCB to presumably solve the damn wiring issues! Very interested to see if it'll work 

Also made some other accessories to toy with, such as an I2S ADC and DAC and a TOSLINK interface, so I can try also S/PDIF or tackle ADAT or what not.

//EDIT: Just spotted a first mistake on the FPGA board. Fuuuuuuck!

[Wiljan]

After taking a bit of break from video and toying with VHDL at other projects, look what we finally got here!

A PCB to presumably solve the damn wiring issues! Very interested to see if it'll work 

Also made some other accessories to toy with, such as an I2S ADC and DAC and a TOSLINK interface, so I can try also S/PDIF or tackle ADAT or what not.

//EDIT: Just spotted a first mistake on the FPGA board. Fuuuuuuck!

Looks good and pretty quick delivery 
Hope the error you have spotted can be fixed and the board still can be used