Understanding Skid Buffer Mechanism

[promach]

I have some questions about http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html

1) Why is skid buffer designed to be 2-entries FIFO instead of just 1-entry FIFO ?

   

However, pipelining handshaking is more complicated: simply adding a pipeline register to the valid, ready, and data lines will work, but now each transfer take two cycles to start, and two cycles to stop.

2) Quoted from the article , why two cycles to start, and two cycles to stop ?

[OwO]

You could make a 1 entry skid buffer:
https://zipcpu.com/blog/2019/05/22/skidbuffer.html

but as the skid buffer itself adds a slow mux to the datapath you need one more register to achieve good timings

[promach]

skid buffer itself adds a slow mux to the datapath

What do you exactly mean by slow mux ?

The goal of the skid buffer in Fig. 1 is to bridge the divide between combinatorial logic on the one side and the registered logic on the other–given that the outgoing stall signal (i.e. !o_ready) can only be a registered signal.

In the zipcpu blog article you linked above, why the outgoing stall signal (i.e. !o_ready) can only be a registered signal ?

[OwO]

On an FPGA the mux adds one LUT to the data path and adds delay. It's not the LUT that's slow, it's routing the signal from unrelated logic that is possibly far away, so you will want to register it first before doing anything.
Ideally all outgoing and incoming signals should be registered for best performance.

[promach]

However, it seems like skid buffer is way too over-simplication of my situation with external memory.

Note that RREADY of AXI master is asserted low for more than few clock cycles which could be due to interconnect priority arbitration or due to destination cache storage is full

Therefore, skid buffer which could just store two entries might not be enough.

But I suspect that skid buffer itself provides negative feedback signal to ARVALID of AXI master ?

Please correct me if wrong