Understanding Timing Constraints

[netturan]

I've recently started to explore the world of FPGA and it has really been a productive journey so far. I've been writing HDL designs and going through different resources so far.Now that I've got my first FPGA I've decided to test my design finally.I've been reading about how I need to look into more details regarding timing and I wanted to know what exactly do I need make sure that my design works.

1. My design has a communication interface that takes in commands at a faster clock and sends triggers to my design to execute it. For this I have written up 2ff synchroniser that toggles everytime a command is to be executed.( Something I read up about clock domain crossing, don't know much)

2. Another part of my design has an edge detector that detects an edge in a non clock signal using a delay register

Keeping this in mind what should be my goal while writing timing constraints ?

[rstofer]

https://www.doulos.com/knowhow/fpga/synchronization-and-edge-detection/

I have written some fairly complex projects and never worried about timing.  I specified the clock rate and symmetry and the tool (Xilinx ISE or Vivado) took care of everything else.  Of course, I was only running at 100 MHz.  Maybe if I pushed the speed envelope things would be different.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug903-vivado-using-constraints.pdf

There are videos re: the Timing Constraints tool.  Google for 'xilinx vivado timing constraints'

[netturan]

Well my internal logic is being run at below 10MHz but the part that I'm worried about is if there will be any issues when  the communication interface(JTAG) works at a drastically higher frequency.

[rstofer]

I don't see how the IO portion of your gadget is going to run faster than the system clock.  Sure, you can run the logic at a submultiple of the system clock but, in the end, everything needs to be synchronized to the system clock.  There are usually clock managers on-chip for the very purpose of creating phase accurate (sub)multiple clocks.

But I still don't see how the internal logic, running much slower than the JTAG IO, is going to work.