USB3320 Device not able to detect with Zynq RFSoC

[LakshmiN]

Hi Tom66
Yes we are using USB 3.0 also,
But as of now, USB 3.0/Super speed signals not initialized in device tree. Only concentrating with USB 2.0
Yes, In design we have made sure that VDD 1V8 will come first and then VDDIO 3.3V
I had also attached the PCB trace lengths in mils, Please look into them once.

[tom66]

Trace lengths ~4.7" total, and DATA7 seems oddly shorter than the rest.  Overall, the bus is longer that I would want.  I have heard a general rule of 2" / 5cm max for ULPI unless you really know what you are doing.

The biggest headache with ULPI and longer trace lengths would be the lane turnaround scenario where the FPGA transmits against the clock supplied by ULPI transceiver.  So total latency would be ~10" PCB track, or approx 1ns, clock period of 60MHz is ~16ns, so I suppose it is possible it could slightly marginalise your setup or hold time.  However this is just a guess, I am not intimately familiar with the ULPI standard at the physical layer.  You would be able to test this using an oscilloscope, but as mentioned it needs to be fast enough so that the bandwidth of the scope does not limit your measurement.  Also, it is possible at such long trace lengths that the impedance matching of the interface becomes more of a problem.  The general rule for impedance matching is that your line should be matched if the maximum wavelength exceeds 1/10th the length of track.  You are right up against that limit, especially if you consider referencing to a clock from the ULPI receiver.

Edit: clarification

[asmi]

I didn't see anything obvious on a schematics, the only thing I can't check is if SoC pinout is correct, please double-check your MIO config to make sure it matches what you have on a board.

[LakshmiN]

"I have heard a general rule of 2" / 5cm max for ULPI unless you really know what you are doing." ---  I've seen in ZCU216 evaluation board trace length upto 6" inches.
SoC Pinouts are correct

[SiliconWizard]

To get setup or hold time issues at 60MHz you would need to seriously screw up the routing. If you couldn't get this right, I wouldn't want to see what you've done with your DDR RAM.

[AndreZheng]

Is the 5V VBUS on J7 header available or not?

[LakshmiN]

Yes, At J7 USB connector 5V is available