Use Microsemi/Microchip IGLOO in new design, will they have future ?

[Miyuki]

I have a question
Is it a wise idea to use IGLOO device in new design ? They are arounds for long times, and swtill are marked as active even now stocks are really scare at distributors. But are only device of this type on market today.
This brings me a worry. Is it just a temporary glitch or will be here problem with availability in future ?

[EverydayMuffin]

Microchip/Microsemi's longevity statement for the IGLOO is at least 10 years from 2020, so these devices are fine for new designs.

Which IGLOO device are you looking at? Have you looked at IGLOO2?

[Miyuki]

I need something like AGL250 or AGL400
It is much closer to Lattice ICE40 than to IGLOO2 they are huge

[EverydayMuffin]

I need something like AGL250 or AGL400
It is much closer to Lattice ICE40 than to IGLOO2 they are huge

The device you mention, AGL400 in CS196 (8x8) is the smallest package device from Microchip at 5K LEs.

At 3K LEs, you could also look at the IGLOO nano AGLN250 in CS81 (5x5) as an alternative to AGL250.

But you're right, IGLOO2's packages are bigger, the smallest package is FCSG325 (11x11).

[SiliconWizard]

I need something like AGL250 or AGL400
It is much closer to Lattice ICE40 than to IGLOO2 they are huge

Do you have a particular reason for avoiding the iCE40 series?

[Miyuki]

IGLOO have little lower static power, but are much faster
ice40 have slow internal ram and so

[woofy]

IGLOO have little lower static power, but are much faster
ice40 have slow internal ram and so

Maybe we are looking at different data sheets.
I see igloo ram working at 160MHz (DS0095 page 2.117)
and ice40HX at 403MHz (FPGA-DS-02029-3.5 page 29)

[ebclr]

A plus for ICE40 devices, is that you can use opensource tools

[SiliconWizard]

IGLOO have little lower static power, but are much faster
ice40 have slow internal ram and so

Maybe we are looking at different data sheets.
I see igloo ram working at 160MHz (DS0095 page 2.117)
and ice40HX at 403MHz (FPGA-DS-02029-3.5 page 29)

Depends on the iCE40 series you're looking at, I guess. The HX is not the lowest power of the iCE40, and it looks like the OP is looking for low power (especially static power).
I'm not 100% sure, but IIRC, some of the MachXO2 (/ZE) models have similar static power, and also have internal flash and a "standby" mode. They are slower than the IGLOO though and much smaller in LUTs. If I'm not mistaken, all iCE40 require an external flash chip.

According to EverydayMuffin, you have 10 years ahead, so that's probably good enough for a product unless you're targetting medical devices or military stuff.
One thing to note is that the future of the IGLOO series itself is unknown, if that matters. We dont' know much about Microchip's strategy. The IGLOO2 (that was before Mircrochip), AFAIR, already was not as interesting as the IGLOO in terms of power draw, so we could sense a shift in strategy.

[mon2]

Many of the Lattice devices feature an internal OTP (NVCM) memory to boot your IP. Just do be careful to review the voltage at which the OTP must be programmed. For example, for the ICE40UL1K, the NVCM_Vpp must be +3v0 (not +3v3) for proper programming. This issue was raised and answered by the Lattice support FAE and they insisted of this max value.

After programming, ok to operate the FPGA @ +3v3.

We have confirmed that the CRAM (configuration RAM) of the Lattice ICE40UL1K devices can be configured through an external SPI master (ie. FTDI with MPSSE); using an external SPI flash device (many models are supported but be sure to review the Lattice notes on the requirements - standard SPI flash that must obey specific but common SPI commands) and finally boot through the internal OTP.

The decision how to boot is defined by an external pull-up or pull-down resistor on the SPI_SS line. If HIGH upon power up, the OTP is investigated by the FPGA - if blank then expects the booting from an external SPI master (FTDI). If OTP is programmed, the OTP is used as the boot source. If this external resistor is a PULL-DOWN, the FPGA will only boot from the external SPI bus master.

Please see attached from their TN1248.