Using ULPI USB PHYs for custom data links

[SiliconWizard]

(Just a little note about the ICE40UP: the 5K version has 5280 LUTs, 120Kbits of EBR and 1024Kbits of single-port RAM, with IOs working up to 250MHz. No need to get obsessed with this example of small FPGA I gave though. This was just a possible choice, not the only considered choice.)

People interested or curious about multi-channel audio can have a look at current standards, such as AES10. But AES10 could still be extended.
As a quick example, say you have a stream of 32 channles of 32-bit, 192kHz samples, that's about 25 MBytes/s. 64 channels, and you're close to the maximum bandwidth. Add some additional data within the stream, and it goes up. Etc.

Another quick example, since I talked about data acquisition. Say you have 8-bit samples @50 MHz sample rate to transmit over a single pair. With some overhead and maybe a few additional packets, and you reach the maximum bandwidth. Can you do it with an iCE40UP? Absolutely. It would take something like 10% of the total LUTs at maximum, actually. So a lot of room to spare for additional features.

For audio applications, getting as many samples as per the first paragraph using an iCE40UP and directly from ADCs would be challenging or impossible, but it could be aggregating input streams with lower bandwidth and transmit it all aggregated on a single pair. Is it doable with an ICE40UP? Absolutely.

Lastly, nobody said you had to use the full bandwidth of the link at all times. The whole idea of portability is that you could reuse the same bus for various applications and various "nodes". A given node could be using a small FPGA and transmitting only a few MBytes of data per s, while some other nodes could be aggregating data and transmit it using more bandwidth, using beefier FPGAs if required, especially if there is additional processing to be done.

[Chris Mr]

I read most of the posts and wondered if you had considered SPE (Single Pair Ethernet).  It's full duplex and up to 1Gbs.

Maybe not as cheap as the USB but hey - super simple to get going.

[SiliconWizard]

I read most of the posts and wondered if you had considered SPE (Single Pair Ethernet).  It's full duplex and up to 1Gbs.

Maybe not as cheap as the USB but hey - super simple to get going.

I did mention gigabit Ethernet as an alternative, but I don't know much about SPE yet. I'll have a look at that.

[jeremy]

You might find this useful: https://github.com/cliffordwolf/PonyLink

[SpacedCowboy]

Resurrecting an old thread

Did you actually get anywhere with this ? I find myself in a similar situation where I want to transmit a fair amount of bandwidth over a 1-2m or so cable. I remembered the thread, came back to it, and started to read the ULPI spec, and it does actually sound eminently do-able - sync to clk60, obey the STP/NXT and direction-change requirements, prepend data with a byte to identify what to do with it, and ... that's more or less it for transmit ... Receive is similar and maybe even easier...

Given that the parts cost of the rest of the components is all under about $15 (and the FPGA being half of that), I'm loathe to go spend a fortune on high-speed line drivers. 480 mbps for $1.70 or less seems pretty good...

[SiliconWizard]

I had to put this project on hold, but I'm definitely going to get back to it shortly.
Didn't see any possible showstoppers either. ULPI PHYs are pretty flexible.

[Forty-Bot]

I read most of the posts and wondered if you had considered SPE (Single Pair Ethernet).  It's full duplex and up to 1Gbs.

Maybe not as cheap as the USB but hey - super simple to get going.

I think any kind of ethernet phy would work. OP said earlier that they only need 50 MB/s in either direction, which is well within the capabilities of 100BASE-TX. I did some brief searching, and the cheapest (non-obsolete, in-stock) transceivers right now are

• $1.60 USB 2.0 https://octopart.com/usb3317c-cp-tr-microchip-24995458
• $1.40 100BASE-TX https://octopart.com/lan8720a-cp-abc-microchip-75448787
• $2.80 1000BASE-T https://octopart.com/vsc8531xmw-02-microchip-96774388

So there's not that much difference in price between the sub-1G transceivers. IMO Ethernet is nice because you get full duplex and it's easy to use the existing protocol and retain interoperability with other equipment (useful for development/testing). If you do end up using a custom (non-Ethernet-conforming protocol) with an Ethernet phy, keep the following in mind:

• You must start the frame with 0x55, 0x55, etc. Technically you don't have to, but often the first byte(s) of a transmission won't be encoded, and the receiver will insert 0x55 automatically.
• You must insert a 12-byte IPG (that is, deassert TX_EN) every 2000 bytes. This is necessary to maintain synchronization between the phys and to prevent any internal FIFOs from overflowing. Your phy may support jumbo frames, but read the datasheet.

Similar restrictions probably apply to USB as well, but I'm not as familiar with that standard.

[SpacedCowboy]

Using plain-old LVDS is fine for board->board connections (and I have a project on the go that does that) but I'm kind of leery about pushing raw LVDS over a 2m cable without some sort of PHY there.

I've nothing to back that up, I've never done it before, but my gut tells me that's pushing the envelope a bit. Now I'm not an EE, just an aging physicist - and perhaps I ought to be less reliant on gut feeling, but FPGA pins <--> LVDS over cable <--> FPGA pins seems ... optimistic.

Also worth noting (I don't know about @SiliconWizard) that I'm using very cheap FPGAs, in the $9 ballpark. I get 800Mbps LVDS with some SERDES attached, but I don't get high-speed transceivers, and the max capacitive load on the LVDS pins is specified as 10pF.

As for price, 100-BaseTX is going to be slower (but I take the point about duplex) and 1000-BaseTX is roughly twice the cost. Again, just speaking for myself, that's significant when the rest of the components are so cheap.

In fact, my interest in it as a technique is waning though, because I switched some stuff around, and now I don't need to actually send the high-volume data over a link at all - the best link is one you don't need at all There'll still *be* a link, but it's sufficiently low bandwidth that the built-in USB port on the RP2040 that's booting the FPGA will do just fine