Electronics > FPGA

Verilog automatic one-hot encoding for state names

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rstofer:
In VHDL, I might create a type for state names and just populate it with labels.  The tool will automatically assign one-hot values for each state and I never need to deal with the actual value.  Of course 'state' and 'next_state' can get pretty wide but that's the cost of not having to decode values.



--- Code: --- type state_type is ( s0,  s0a, s0b, s0c,
                             Fetch,  s1a, s1b, s1b1, s1c,
                             s2 , s2a, s2b,
                             s3,  s4,  s5,  s6,
                             s7a, s7b, s7b1,s7c, s7d,

                             ...     

                             MemWr, MemWr1);

--- End code ---
[/font]

There might be a lot of states (I left out a LOT!) and manually assigning values in Verilog seems unworkable.  So, how is it done in the real world?

I have also been known to define the states in a VHDL package file.  Maybe a Verilog 'include' file?

BrianHG:
Have you just tried using actual 'strings' , IE just name each state to it's actual name?
It can make debugging a complex machine easy to read.
Apparently Modelsim and Quartus (with a few warnings, IE a limit on character lengths) appear to work with strings.

julian1:
verilog enums?

https://verificationguide.com/systemverilog/systemverilog-enum/

Bassman59:

--- Quote from: rstofer on January 24, 2022, 03:26:41 am ---In VHDL, I might create a type for state names and just populate it with labels.  The tool will automatically assign one-hot values for each state and I never need to deal with the actual value.  Of course 'state' and 'next_state' can get pretty wide but that's the cost of not having to decode values.

--- End quote ---

System Verilog allows you to create an enumerated type like VHDL has offered since the beginning.

BrianHG:

--- Quote from: julian1 on January 24, 2022, 08:42:30 pm ---verilog enums?

https://verificationguide.com/systemverilog/systemverilog-enum/

--- End quote ---
Learn something new and useful everyday.

Sort of like recently when I found the little ' $bits (packed typedef structure) ' to return the number of wires inside my structures to easily feed one of my structures in-out through a Quartus FIFO using the $bits to set the fifo's width without worrying anytime I add or remove buses inside my typedef feeding the fifo's data-in -> out port.

The $bits() works with any logic, wires, array, structures, and it should also be functional with enum.

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