I want to do 3 operations in 3 different clock cycles, data in, addition and multiplication and repeat. Can anyone give me a Verilog template to implement the above? Something like this pseudocode:

`always @(posedge 1st clk or negedge rst)`

if (~rst)

a <= 0;

else

a <= data_in;

always @(posedge 2nd clk or negedge rst)

if (~rst)

b <= 0;

else

b <= a + c;

always @(posedge 3rd clk or negedge rst)

if (~rst)

d <= 0;

else

d <= a * b;