Verilog coding style guidance needed

[blackblade]

I want to do 3 operations in 3 different clock cycles, data in, addition and multiplication and repeat. Can anyone give me a Verilog template to implement the above? Something like this pseudocode:

Code: [Select]

always @(posedge 1st clk or negedge rst)
if (~rst)
a <= 0;
else
a <= data_in;

always @(posedge 2nd clk or negedge rst)
if (~rst)
b <= 0;
else
b <= a + c;

always @(posedge 3rd clk or negedge rst)
if (~rst)
d <= 0;
else
d <= a * b;


[fourfathom]

What is the phase relationship of these three clocks? 

If these clocks are all derived from one common clock then (depending on speed) your task is probably easy.  If these are random clocks then we need to have a long discussion about synchronization across clock domains.

[woofy]

Assuming 1st, 2nd and 3rd are sequential states of the same clock, then you need a state machine.
google "verilog state" and you'll get some useful results.

[blackblade]

What is the phase relationship of these three clocks? 

If these clocks are all derived from one common clock then (depending on speed) your task is probably easy.  If these are random clocks then we need to have a long discussion about synchronization across clock domains.

Yeah, it's one common clock.

[blackblade]

Assuming 1st, 2nd and 3rd are sequential states of the same clock, then you need a state machine.
google "verilog state" and you'll get some useful results.

What do you think would be better? A counter or a state machine?

[BrianHG]

Here is the dumb method using simple counter and an if() to run multiple actions in order, in this case to consolidate a single multiplier and single adder to accumulate a number of math operations on many input sources together:

Audio mixer-filter lines 73-170

(The important part is highlighted in yellow at the bottom..)

Here is a complete lesson I have given another user on how to setup a state machine using the case() statement:

https://www.eevblog.com/forum/fpga/fpga-output-not-consistent-with-modelsim/msg4077400/#msg4077400

You will also find attached .zip files with Modelsim setups so you can simulate to see how the code works and how to monitor/debug your state machine.

(It boils down to a case(program_counter), then program_counter = 0 on reset, =+1 the rest of the time while inside the 'case' positions, you can force the program_counter to a unique position or hold it's current position based on an if(), sorta like a goto command.)

[ejeffrey]

Is this pipelined or an operation that takes 3 cycles during which the logic is "busy"?

For pipelined it's easy:

Code: [Select]

always @(posedge clk or negedge rstn) begin
if (~rstn) begin
a <= 0;
                a_d <= 0;
                b <= 0;
                d <= 0;
end else begin
                // Stage 1
a <= data_in;

                // Stage 2
                a_d <= a;   // delay a one cycle to use in stage 3
b <= a + c; // Where did c come from?  Is it constant?

                // Stage 3
                d <= a_d * b
         end
end

If I get any more complicated than this I use a naming convention where all signals are labeled with the stage of the pipeline where they are assigned so that you can quickly verify that all of the assignments for stage N only depend on data from stage N-1.