Author Topic: verilog conditional compilation with several flags in condition  (Read 1897 times)

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Online radiolistenerTopic starter

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I want to use several flags in condition for conditional compilation directive, something like this:
Code: [Select]
`ifdef FLAG1 or FLAG2
// stuff1
`else
// stuff2
`endif

but it seems that `ifdef doesn't support several flags and I don't want to duplicate code for several directives. So, what is the best way to write such condition in verilog?
 

Offline Someone

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Re: verilog conditional compilation with several flags in condition
« Reply #1 on: May 30, 2022, 10:32:01 am »
its a define, one of the few situations where Veirlog has some form of typing:

https://verificationacademy.com/forums/systemverilog/oring-ifdef
 
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