Electronics > FPGA

VERILOG: Equality test with don't cares

(1/3) > >>

Hello,  I’m having trouble getting a simple frequency dividing loop to work. Here’s a minimal test fragment, if the comparison wire has any don’t care bits in it the test fails, if I don’t include them it works fine. I’m obviously specifying the don’t cares in the wrong way, can anyone help?

In case it matters, IDE is Quartus-II.  Thanks in advance

reg [24:0] TBdiv;
reg LEDreg ;

 wire Roll = (TBdiv ==  25'b1111111111111111111111111) ;  // This works
 wire Roll = (TBdiv ==  25'b111111111111111111x111111) ;  // This doesn't

   always @ (posedge clk)
      if (Roll)
         LEDreg <= ~LEDreg  ;  // Test LED
         TBdiv <= 25'd0 ;
         TBdiv <= TBdiv + 25'd1 ;
assign LED = LEDreg ;

What about something like...

wire Roll = (TBdiv{24:7} == 18'b111111111111111111) && (TBdiv{5:0} == 6'b111111);

This might not be exact I'm a little rusty. But basically cutting out the don't care bit by splitting up the comparison

wire Roll = (TBdiv ==  25'b111111111111111111?111111);

I think this is also valid

Try :
wire Roll = (TBdiv ==  25'b111111111111111111?111111) ;

Please double check in your simulator.  I'm a bit rusty in this area.

When placing an 'x', this means your source reg needs to be unknown or un-initialized 'x' to return a high value.  This does not tend to work in FPGA hardware but only in simulators.

Thanks for the comments folks. Since then I’ve done some more testing as well as googling, and now realise that I’ve stumbled on a can of worms. All I was trying to do was to reduce the footprint of the wire by anding only the bit positions that indicate that the target has been reached. I would have thought having convenient syntax available for that function would be a nobrainer, whereas in fact it seems that there are issues all over the place with the notion of ‘don’t care’.

It’s probably good that all this has come to light, up to now Verilog has looked pretty unbreakable. If I ever come across a ‘what would you like added to Verilog?’ website I’ll add that to it, although I have no doubt that it would have already been suggested. Cheers

I'd implement this with a bit mask, ie.

if (value AND mask) = (target AND mask) then <stuff>

This doesn't add any extra logic to the final gate list, because if the mask is fixed, the results of the AND operations are known at compile time - either the original bit value or zero, neither of which requires any additional logic to derive.

The tests for "does 0 equal 0" can also be omitted and will optimise out, leaving behind just the comparison between the bits you're interested in.


[0] Message Index

[#] Next page

There was an error while thanking
Go to full version