Electronics > FPGA

Very small linux capable core

(1/11) > >>

ali_asadzadeh:
Hi,
This could be my first time going for a linux on a soft-core, I want to know if we have open source cores capable of running minimal linux, I have about 10-12K of LUT left on my device, and it's a Gowin part.

Do you recommend any thing? is it possible on 10K LUTs?

brucehoult:
Sure.


--- Quote ---VexRiscv linux balanced (RV32IMA, 1.21 DMIPS/Mhz 2.27 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, catch exceptions, static branch, MMU, Supervisor, Compatible with mainstream linux) ->
    Artix 7     -> 180 Mhz 2883 LUT 2130 FF
    Cyclone V   -> 131 Mhz 1,764 ALMs
    Cyclone IV  -> 121 Mhz 3,608 LUT 2,082 FF

--- End quote ---

https://github.com/SpinalHDL/VexRiscv

ali_asadzadeh:
Thanks for the info, :-+
It's in scala :'( do you recommend anything Verilog or system verilog at least! or do you recommend any good tutorial about scala?
How long does it take to learn scala, since I can do a moderate job on verilog and system verilog.

SiliconWizard:

--- Quote from: ali_asadzadeh on July 25, 2021, 01:59:27 pm ---Thanks for the info, :-+
It's in scala :'( do you recommend anything Verilog or system verilog at least! or do you recommend any good tutorial about scala?
--- End quote ---

It uses SpinalHDL. It's based on Scala so sure, you'll need to learn Scala. And then you can go there: https://spinalhdl.github.io/SpinalDoc-RTD/

But SpinalHDL generates Verilog, so you can read the generated code, although I would expect it not to be extremely readable compared to human-written Verilog.
Also, although probably more comfortable, you don't need to understand VexRiscv fully to be able to use it. Many people have used it without knowing SpinalHDL. You just need to figure out how to configure it for your particular use and generate the HDL output.

Now, it's unclear to me whether VexRiscv is really ready to be directly used for running Linux at the moment outside of pure simulation. Quoting VexRiscv's Readme:

--- Quote ---There is currently no SoC to run it on hardware, it is WIP. But the CPU simulation can already boot linux and run user space applications (even python).
--- End quote ---

Maybe brucehoult can confirm it is possible already, but what the maintainers say sounds confusing to me.

brucehoult:

--- Quote from: SiliconWizard on July 25, 2021, 04:10:12 pm ---Maybe brucehoult can confirm it is possible already, but what the maintainers say sounds confusing to me.

--- End quote ---

I don't have direct experience with it.

The safe choice for SoC is RocketChip. I don't know the minimum size if you cut out FP and so forth. A full single-core system will fit on an Arty. Several real chips are based on the Rocket components, including the SiFive Fe-310 and FU-540, and Kendryte K210.

Again, it's a generator (Chisel this time) written in Scala, producing verilog.

Navigation

[0] Message Index

[#] Next page

There was an error while thanking
Thanking...
Go to full version