That's how I would do it as well.

Just note that you don't formally have to resize both terms of the sum, one of them would be enough (but it's probably more readable to resize both):

When both operands to a binary arithmetic functions + or - are either SIGNED or UNSIGNED, the function

returns a value with the same number of elements (bits) as the larger of the two operands.

This quote is from IEEE Std 1076.3-1997, so that was possible way before VHDL 2008.

But you are right in resizing. You have to resize at least one of them, otherwise the sum would be with the same number of bits as the operands (which is not what the OP asked), and the result would not be 1 bit wider anyway, so you could not assign it to a vector which is 1 bit wider.

Edit: (That's something missing in AndyC_772's code. He also uses arithmetic on std_logic_vector, which I really do not recommend. This was the old Synopsys way. I don't know if the result of a sum would automatically be 1 bit wider with Synopsys' libraries or not...)

Quick notes:

- I think there's a missing "end process" in your code.

- Small bonus: you could avoid the hard-coded slice at the end like so:

`sigout <= std_logic_vector(resize(shift_right(sum, 1), sigout'length));`