Electronics > FPGA

vhdl - how to use memory bits for data storage?

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Can someone please explain this to me??? Using Altera Quartus 13.01, Linux-64 and a tiny EP1C3T144 Cyclone1 FPGA, cheap 35$ board from ebay.

Basically want to use a 256x8 ROM/block RAM as text ROM to display on a 20x2 LCD, so far more for goofing around trying to learn VDHL than for serious application....
ROM/block RAM is initialized from 256x8 mif file
Also using ROM data to blink 6 LEDs at about 10Hz.
The weird thing is that everything is displayed correctly on LCD, LEDs are also blinking accordingly to the data in ROM, yet the report tells me, no block RAM is used.
ROM is present in RTL viewer, but missing in chip planer and synthesis report. No way that thing works on 338LUTs only, either the LUT report is wrong or it's secretly using block RAM without telling me???

Block RAM is reported correctly/present in chip planer if used directly without being inside "if statement", amount of LUTs used changes insignificantly and LEDs blink the same way....

If the ROM is small, or not instantiated correctly, Quartus/Vivado will often just implement it in registers rather than BRAMs.  That may be what is going on here.  Check your synthesis output logs to see whats happening to the ROM during synthesis/implementation

There is zero guarantee the tools will map any memory described in HDL as block RAM. It may or may not, depending on memory size/width, speed constraints, code style (yes, to make the tools infer BRAM, some HDL styles are often required), etc.

I don't know Quartus, but for most FPGAs I've dealt with, there's usually an attribute you can define for your memory to "force" inferring block RAM.

But note that unless it eats up a lot of LUTs/registers, or does not meet timing requirements, you should usually not bother. Distributed memory is fine, and for something that small (256x8), really, you shouldn't bother.

Now are people actually still using Cyclone 1 FPGAs?  ;D (just a question, I don't know how many LUTs they have.)

Just use the wizard to generate the memory you need, then instantiate such module in your design.

Here is the correct google search term:

'quartus vhdl infer ram attribute'

You may tell quartus to infer any array into a ram block of your choice.  Though, make sure that choice will match the FPGA you are compiling for or just try MLAB.


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