Author Topic: VHDL Port Declaration issues in Lattice Diamond  (Read 2762 times)

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Offline MuriTheMythTopic starter

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VHDL Port Declaration issues in Lattice Diamond
« on: February 03, 2024, 05:02:46 pm »
Hi folks:

I'm new to Lattice Diamond and I ran into some weird problem when trying to work in there.

As shown in the picture, the port "clk" and "s" are declared in the same line. But the first script with "clk" in line 17 passed the syntax check, and the second with "s" in the same place failed.

I tried to search online and I still can't see why.

A big thank you for your time and patience in advance.

Sincerely,
Muri
 

Offline SiliconWizard

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Re: VHDL Port Declaration issues in Lattice Diamond
« Reply #1 on: February 03, 2024, 08:17:01 pm »
Shouldn't it be
Code: [Select]
architecture bhv of srlatch
 

Offline coppercone2

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Re: VHDL Port Declaration issues in Lattice Diamond
« Reply #2 on: February 03, 2024, 08:23:24 pm »
I would consider bribing the port authority
 


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