Electronics > FPGA

Video Upscaling and Overscan

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Mario87:
Hi all,

I am working on a project where I am taking in a 720x576, 50Hz, interlaced video feed and then de-interlacing and upscaling to 1920x1080, 60Hz, progressive video to be output over HDMI.

I have used the Xilinx VPSS IP and I have this working really well at the moment. However, the device I am capturing video from is from an era of CRT displays, so there is significant overscaling which results in a black border all the way around the screen.

The systems does not have a DE (active video) signal to feed into the 'Video In to AXI Stream' IP, so I am using the VBLANK & HBLANK signals to tell the IP when the active video is available using the following logic:

active_video <= ~vblank & ~hblank

However, I can see that to fix the overscaling issue I need to use some other method to identify to the 'Video In to AXI Stream' IP where the active video I want to display actually is.

What I was thinking is to generate my own custom VBLANK & HBLANK signals by looking for a fixed point (beginning of HBLANK for example), then counting clock cycles, setting my custom HBLANK high when I need it, counting clock cycles while high, then setting it to low when I no longer need it and repeat.

The same could also be done for VBLANK.

Is that a sound way to go about this, or is there a different, more efficient way? With my way it just relies in a single known point such as HBLANK / VBLANK going high for 1 time, then after that it is just counting clock cycles over and over.

Any thoughts / suggestions appreciated!

NiHaoMike:
For VBLANK, you'll want to count HSYNC pulses instead, but you got the general idea.

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