Virtex-6 Partial reconfiguration

[MexEngineer]

Hello!

I'm trying to understand how to do the partial reconfiguration of an FPGA, I hope someone could help me to get my thoughts straight.

Currently, I'm able to create the project and generate the full and partial bitstreams, I know that those work because I can load the partial bitstreams using iMPACT and it works as intended.

I've read the configuration userguide (UG360) and I understand that I can do the reconfiguration through the ICAP primitive, but can I do it using the IPROG command? Or do I need to load the bitstream from the flash using my own code?

Note: I want to do partial reconfiguration and not full configuration.