Vivado - strategies for resolving timing errors

[JohnnyMalaria]

Hi,

After a few weeks of developing an VHDL design that works as planned in the simulator, I now face my next new challenge - not meeting timing constraints. Although my design synthesizes okay (a miracle in itself), I'm getting timing issues as shown in the attached screenshot.

These are all associated with a Xilinx FFT IP Core and its related DSP slices.

Can you point me to some additional resources that explain strategies for understanding and solving these types of timing problems?

Thanks.

[asmi]

There is no blanket rule applicable for all cases. Open failed paths' schematics and see what's going on there.

In your case it looks like your failed paths contain a lot of levels of logic between FFs, you will probably want to pipeline such long logic chain. Also if you use DSP blocks, make sure you use internal pipeline registers (at the very least the one on the output side), or you will have huge routing delays.

[hamster_nz]

What is the splt between logic delay and routing delay?

Routing delays usually ends up as slightly more than logic delays and you can't make the logic run any faster.

A reasonable assumption is that the  current design, no matter how optimized, will never clock quicker than 2x the logic delays, unless heavily leveraging the underlying FPGA architecture.

[NorthGuy]

You have too much combinatorial logic and this causes delays. You have 10 levels.

There are 3 ways.

1) Pipeline. That is, split your combinatorial logic, so that only few levels need to execute during the single clock. For example, instead of doing 10 levels in one clock, do 3, 3 and 4.

2) Decrease your clock frequency. It doesn't run at 100 MHz, but should run at 40 MHz just fine.

3) Re-think and change the design.

[JohnnyMalaria]

Thank you all for your suggestions. I'm happy to report all timing constraints are now met

My design includes four Xilinx Multiplier IPs used to calculate the squares of the real and imaginary output from the FFT. I increased the level of pipelining from zero to 5.

Another good learning experience.