Electronics > FPGA

VUnit, UVVM, OSVVM: What are similarities and differences?

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I guess I cannot really be neutral when it comes to UVVM vs OSVVM (or Vunit), so I will not comment on that, but only comment on why a VHDL verification methodology may be your best choice.

I think it is important first to evaluate where people spend time on verification. So, first of all, according to Wilson Research, half the verification time is spent on debugging. That means the debuggability / debug support is critical, and the best way to reduce debug time is to have a very good testbench structure and easily understandable high level commands. Making a component oriented very structured TB architecture is really simple in VHDL, and in UVVM it is a bit like Lego. But the time spent here is not necessarily very significant. What really *is* significant is the time you spend developing, debugging and running your many test cases. This easily constitutes 60-90% of the total verification workload.

Here, good VHDL verification methodologies are as good as any other more modern software oriented language. The following test case lines from UVVM show that even SW designers can easily both understand and write FPGA test sequences:

axilite_write (REG_INTERRUPT_ENABLE,  AXISTREAM_IRQ, “Enabling AXI-S interrupt”);
axistream_transmit (v_byte_array, “sending packet ***”);
axistream_expect (v_byte_array, "receiving packet ***";
axilite_check (REG_INTERRUPT_STATUS,  AXISTREAM_IRQ, “Receiving AXI-S interrupt”);

The byte array illustrated here could of course be any size, as the parameter of the procedure is unconstrained. The example shows overloads where the actual signals are not included, but this would be similar in any sensible approach.
Good sequential sequences like this are simple to write in any methodology, but accessing these interfaces simultaneously requires a more structured testbench, and UVVM allows simple control of such testbenches as well, thus providing a great means for detection of cycle related corner cases.

There are in fact many similar error prone digital design aspects of FPGA design that most SW designers would never search for. A VHDL testbench with concurrent procedures, processes or verification components – organized in a very structured architecture, such as the Verification components of UVVM would handle this better than any existing non-HDL oriented languages or methodologies.

You can find more information under : https://emlogic.no/uvvm/


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