Electronics > FPGA

What am I doing wrong?

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lawrence11:
So I am looking at this garbage video and trying to do the same as him.



@ 27:30, he starts dabbling in a input .txt file, wich is ridiculous path the way he writes it down its so painful and time consuming, I was under the assumption that I could just name this file only with .txt and have it in the same folder and I would be good? Seems like he has valid data in his sim and not me.

Here is my setup, what am I missing?

lawrence11:
Is my pathing wrong?

lawrence11:
Ok never mind this garbage tutorial.

But I have tried other things and cant make it work, :(

Can anybody show me how in Quartus Prime free edition they implement $readmemb and their file pathing?

rstofer:
Tried Google?

https://stackoverflow.com/questions/37135859/in-verilog-im-trying-to-use-readmemb-to-read-txt-file-but-it-only-loads-xxxx

This may help.  You can specify the complete path to the file if you wish.

SiliconWizard:

--- Quote ---What am I doing wrong?
--- End quote ---

Maybe relying on "garbage videos" (as you qualified it yourself) without bothering to look up for further information elsewhere?  :horse:

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