Once upon a time CPLDs were a middle step between PLA/PAL type devices (basically a bunch of or/and gates with n inputs and outputs, that could be connected more or less at will) and FPGAs....
They had the same high level structure as an FPGA but used The AND/OR matrices as a base for the logic block, as opposed to Look up tables.
The biggest difference between the two classes of devices (still somewhat relevant today) is that FPGAs are practically always volatile, requiring bitstream load at each boot from an external memory, while CPLDs are non volatile, and once programmed they start immediately
Nowadays the demarcation line is is blurring quite a bit, usually the modern “CPLDs” (intel Max 10 are just very small FPGAs with an internal flash memory (it can even be a separate die in low end chinese stuff); off the common manufacturers, Xilinx discontinued all non FPGA products, intel has the max line on FPGAs in disguise (max II max V and max 10). Lattice semi has both non volatile FPGAs and true CPLDs(isp4000) and both are referred genetically as CPLDs.
As for the speed advantage,I am not sure it is so relevant with current devices as FPGAs can support frequencies in excess of 400 MHz (I guess CPLDs now seem faster as what you can fit in them are tiny in comparison even with the smallest spartan 7
EDIT: As an example, you can cram a pwm generator for an NPC inverter in a max 5 cpld(the biggest) if you Squeeze hard enough and do not go crazy with features (such as multiple counters for phase shifted carriers)