What are FPGAs used for today and with what tools?

[peter-h]

I did a load of Xilinx FPGA work in 1992-1996. X2000 X3000 and almost got into X4000 but didn't need them because the 3090 did the job.

The tools were Viewlogic 4 (crippled for Xilinx part libraries only) and XACT 5. The code was loaded into a parallel EPROM or a serial EEPROM and the FPGA booted from that.

VL4 ran under DOS 6.2 and supported only specific video cards. The best was an 8514 (1024px wide) emulating one from ATI.

Like all CAD software from that era, the DOS versions were way more usable than the windows versions and that remained the case for a good 10 years, with the windows stuff being buggy as hell. Orcad SDT/386 is still my sch tool of choice, along with Protel PCB 2.8 which is a win3.1 app from 1995; all runs fine under a WinXP VMWARE VM

The software was dongled via the parallel port. VL4 had its own dongle, and XACT5 had its own dongle. The two dongles plugged into each other and were quite easy to break off.

The software cost about USD 20k.

One of the dongles broke and Xilinx said I have to buy all new software - about 10k. I found a solution for that situation on the web (a Russian guy published a patch) but got out of the business ASAP.

What I eventually realised was that while FPGAs were super for prototyping ASICs (or digital parts of mixed ASICs) and I did a lot of that work eventually, most of the projects which resulted in them used in a product could have been done with a fact microcontroller

- for much less money (FPGAs were always premium priced)
- with much more futureproof tools (good luck running the dongled VL4 and XACT5 in a DOS 6.22 VM under win7-64 ) i.e. an assembler / C compiler
- with much more complex functionality

I saw one could eventually get CPUs (8051 type etc) in FPGAs but a device that was big enough was eye wateringly expensive.

One of the projects was a specialised waveform generator which had 64 XC3090 devices on a PCB. At some 5 digit price it was lucrative Could it have been done with a micro? Yes, by computing the values to go into an SRAM whose output would drive a DAC.

What's changed?

[OwO]

These days FPGAs are competitive with microcontrollers and will do far more at the $5 price point. In one application I need to process ADC data at 10-20Msps. A spartan 6 does the job nicely for $4, but a MCU that can handle the data rate would cost more and be ass to work with. I *really* do not like dealing with realtime MCU based systems because they simply do not multitask. Even with everything handled by DMA or peripherals, interrupt handlers still have undeterministic latency because other (necessarily) higher priority interrupts need to get called first. You just simply can not have two independent processes in a MCU without them interfering. On an FPGA this is trivial. The ADC DSP part can never slow down e.g. USB data transmission because they are independent circuits. I can time things to happen at exact clock cycles which happens to be extremely important in some types of test equipment.

[asmi]

What's changed?

In short - everything. A lot of entry-to-mid level FPGAs now cost reasonable money, and they are supported by free tools provided by the vendor. Now a hobbyist can afford to design a multilayer FPGA board, have it manufactured and assemble it without it costing an arm and a leg. The FPGA board I linked in my signature can be ordered and assembled for about $100 - and this is a 4 layer board with 0.1 mm (4 mil) traces and controlled impedance. You probably know all too well how much that would cost, say, 10 years ago.

[dferyance]

FPGAs also do well on tasks that are very parallel. Some of this overlaps with the work done on GPUs though too. OpenCL supports both GPUs and FPGAs for this reason. Some of the big-name datacenters have done work incorporating these into their infrastructure. So not only are they still used, this is an area that may grow. The difficulty I see with this is that the current software trends have moved so high-level that it probably won't be used much outside of some very specialized applications.

The challenge I see with FPGAs is expertise. Using a standard microcontroller with a common toolchain means there are a lot more engineers that can jump in and understand and work on the code compared to a very custom FPGA design using one of the different proprietary and complex toolchains (and often specific version of the toolchain). Of course part cost can be an issue too.

The trend to incorporate more hard features into FPGA is very interesting too. ARM cores, DSPs and memory controllers all in a FPGA package. This can mean using the FPGA mostly outside of the programmable logic world.

[laugensalm]

The times they are a changing..
Nowadays you can also go fully OpenSource with the tools, from bottom to top, hardware and software and bake your hype-riding RISC-V or whatever your favorite architecture is onto a rather cheap die. But I remember the times when a C compiler for the Atari ST cost 5kUSD. Now we have gcc, yosys, allowing us to generate a full processor with special peripherals using 'make all'.
I wonder where the next big paradigm shift will be. Maybe in us all planting potatoes instead of building toys?

[FenTiger]

Some of the big-name datacenters have done work incorporating these into their infrastructure. So not only are they still used, this is an area that may grow.

This area is growing. It's a bit light on technical detail, but Xilinx are doing all sorts of work in this area, with newer designs that are specifically intended for data centre use: https://www.xilinx.com/applications/data-center.html

(Disclaimer: my employer was bought out and incorporated into this group last year.)

Also growing are alternatives to programming FPGAs using RTL; toolchains which can compile (subsets of) C or other "software" languages to FPGA fabric are now available.

[AndyC_772]

Nowadays you can also go fully OpenSource with the tools, from bottom to top, hardware and software

Has anyone yet addressed the issue that only the manufacturer has the timing model for the die, and that without it, you can't be certain that any logic will actually meet setup and hold requirements?

I've just spent an afternoon chasing a stupid, unhelpful Quartus bug, so I'd quite like to look into alternatives - but without the ability to guarantee that my designs meet timing, any alternative software would be unusable.

[SiliconWizard]

Nowadays you can also go fully OpenSource with the tools, from bottom to top, hardware and software

Has anyone yet addressed the issue that only the manufacturer has the timing model for the die, and that without it, you can't be certain that any logic will actually meet setup and hold requirements?

I've just spent an afternoon chasing a stupid, unhelpful Quartus bug, so I'd quite like to look into alternatives - but without the ability to guarantee that my designs meet timing, any alternative software would be unusable.

Agreed. And then there's also the use of internal and undocumented features that can make it all a lot more efficient. Whereas I have absolutely no problem using open source tools for development on MCUs/CPUs (which most are documented well enough so that's no problem), I would personally never use an open source tool for FPGA development unless said FPGA was itself open source. Much too complex and proprietary, and as you said, IMO impossible to even model correctly as far as timing goes.

[asmi]

The times they are a changing..
Nowadays you can also go fully OpenSource with the tools, from bottom to top, hardware and software and bake your hype-riding RISC-V or whatever your favorite architecture is onto a rather cheap die.

Lol. Have you seen any open source FPGAs out there?

[free_electron]

Viewlogic. the horror .. I used that on Sun workstations ... (xilinx tools)

now the tools are basically free (unless you need the latest greatest bazillion gate fpga).
download is using a cheap cable.

tools still support schematic as well as verilog / vhdl

what has not changed is that the xilinx tools still suck ... Altera is much better.

[laugensalm]

Nowadays you can also go fully OpenSource with the tools, from bottom to top, hardware and software

Has anyone yet addressed the issue that only the manufacturer has the timing model for the die, and that without it, you can't be certain that any logic will actually meet setup and hold requirements?

If you know the technology and the topology through reverse engineering, you can get a pretty safe estimate for the routing costs, in fact you can grab that data from the existing tools. I've run a few critical designs through yosys so far, optimization isn't always as good as the vendor's toolchain but it gets quite close.
So far I'm quite amazed how easy it is to track down problems, compared to Diamond or Vivado.

And yes, you could consider some FPGAs so far reverse engineered that the term 'open source' might apply, but let's not count peas here..
We normal folks don't get timing accurate models for uC either, and reports on chip/design anomalies tend to get sparse these days.  So I personally find it easier to debug issues with FPGAs these days, having a full model of the system (I've burnt a lot of time on flaky silicon as early adopter...)

[daqq]

What's changed?

In short, welcome to a wonderful new world. You'll like it since you can appreciate the change.

Highlights:
- The tools for the lower to middle end devices are free.
- The lower devices are very powerful, the middle are insanely powerful and the top of the line devices are insane.
- The lower to middle devices are reasonably priced, with plentiful cheap development board.
- There's more devices and manufacturers with a wide range of capabilities, from physically small FPGAs (3x3mm) with integrated configuration memory, to basically supercomputers on a chip (UltraScale+ VU19P). Add to that serious ARM processors available on the same chip and you've got no end to your options.


edit: As to the applications, I use it for realtime chewing of several streams of 100Msps ADC data, among other things. The chip itself costs ~25 USD. There is absolutely no microcontroller that could do that.

[NiHaoMike]

Open up a modern high end inverter (especially one with fancy features like bidirectional operation/ "AC coupling") and there's a good chance it will have a small FPGA or CPLD to assist with the low level controls.

[free_electron]

Open up a modern high end inverter (especially one with fancy features like bidirectional operation/ "AC coupling") and there's a good chance it will have a small FPGA or CPLD to assist with the low level controls.

of course it has. you wouldn't trust your H-bridge to buggy , time indeterminated, nested loops would you ?

[SiliconWizard]

Open up a modern high end inverter (especially one with fancy features like bidirectional operation/ "AC coupling") and there's a good chance it will have a small FPGA or CPLD to assist with the low level controls.

of course it has. you wouldn't trust your H-bridge to buggy , time indeterminated, nested loops would you ?

Actually some switching power supplies are controlled by MCUs, which is in itself a definite market for some MCU vendors.

I personally wouldn't use them and wouldn't trust software for this either, but apparently some do.

[Kjelt]

Just to add, some microcontrollers for special tasks such as motordrivers have a small dedicated piece of state machine hardware that runs independently of the processorcore.
The software can set the timings , influence the statemachine etc. but it can run alone. Kind of a hybrid model, I hope to see more of this, we are used of adding a microcontroller core to a large FPGA but a small FPGA added to a microcontroller would also be great for some cost and boardsize efficient projects (IMO).

[peter-h]

This is very interesting stuff; thank you all

Yes of course for applications where you need "instant" or parallel actions, hardware is the only solution. But many of these can be worked around; often a uC with a bit of external hardware is a good solution. For example many years ago I implemented a high speed parallel port which had a low average speed but a high burst speed, with a cheap FIFO chip next to the uC.

I would still be concerned about projects which need to be revisited many years later. This became a huge problem with Xilinx. And we did get such cases; one highly valuable custom project (well into 5 digits) came up 15 years later. It would have been difficult to set up the software again (not least because I sold all the floppy disks and the two dongles on Ebay, but actually I had backups, and cracks for the software ) but luckily we had the original master EPROMs with the FPGA code and the customer didn't want any changes. The XC3064 devices could still be found after 15 years (perhaps 20-25 years after introduction by Xilinx) like most chips can be, from old stock vendors.

As a funny aside, I had to implement a state machine, and the only way was to do it in CUPL (a compiler for PLDs like the 22V10) targeting a 22V10 or some such, and then using a converter to convert the resulting equations into logic (schematic) which was a Viewlogic feature, and that piece of schematic was merged with the rest of the project.

For one ASIC project I had to generate a load of test vectors for the final chip. So I did some simulations in ViewSIM (the VL simulator, IIRC) but you could not export the data in the Xilinx-crippled version (actually the program simply deleted the files) so I would exit the program and undelete the files from the DOS file system

Now I am involved with a project which uses a 150MHz ARM... That has a ton of support for driving motors and such. The manual is some 2000 pages.

[tggzzz]

I *really* do not like dealing with realtime MCU based systems because they simply do not multitask. Even with everything handled by DMA or peripherals, interrupt handlers still have undeterministic latency because other (necessarily) higher priority interrupts need to get called first. You just simply can not have two independent processes in a MCU without them interfering.

Not true - the XMOS xCORE devices have up to 32 cores (4000MIPS) and a decent comms fabric.

That enables guaranteed i/o timing/latencies and guaranteed instruction times down to 10ns resolution. The IDE inspects the optimised binary code to determine all the code path lengths between two points, and shows all the timings.

Alone amongst processors, there is a software environment that is designed assuming multicore parallel processing. It is based on 40 year old concepts (CSP), some of which are belatedly appearing in other languages such as Rust and Go.

[tggzzz]

edit: As to the applications, I use it for realtime chewing of several streams of 100Msps ADC data, among other things. The chip itself costs ~25 USD. There is absolutely no microcontroller that could do that.

The XMOS xCORE processors probably could: 32 core, 4000MIPS, guaranteed i/o and instruction timings, no interrupts, no cache.

[tggzzz]

Not true - the XMOS xCORE devices have up to 32 cores (4000MIPS) and a decent comms fabric.

The XMOS xCORE processors probably could: 32 core, 4000MIPS, guaranteed i/o and instruction timings, no interrupts, no cache.

XMOS was marketed as FPGA replacements. They really can't be considered as your traditional CPUs.

Who cares how they were marketed; that's of zero importance.

If you want to claim they aren't traditional CPUs, you will have to define your specific meaning of "tradtional" and "CPU", so that others can understand what you are (and aren't) saying.

They are traditional register-based CPUs: you write programs (in xC/C/C++) that are converted into sequentially-executed instructions. The conventional IDE allows you to single-step through the program at the statement or instruction level, and inspect the values of variables.

Of course they are more than merely that - hence their uses in hard realtime systems.

[UA3MQJ]

FPGAs are now available to Amateurs. And that's great! Now it is more likely to rely on your own experience/knowledge/free time than on the limitations of the FPGA. But this is me from personal experience and experience using Altera. For Altera's available Сyclone FPGA Board with the number of cells from 2000 to 15,000 or 20,000! With built-in PLL and hardware multipliers. In Amateur radio there are many DUC type transceivers with direct digitization of the radio air signal and further processing in digital (heterodyne, filters).

Му boards.


Altera: 2хEP4CE6, EP4CE10, 2xMAXii EPM240, EPM3064.

[ebclr]

I'm working with anlogic fpga,  the the tool i'm using is quite outdated, but is impossible to download a new version from http://www.anlogic.com/down.aspx?Id=13&TypeId=13&fid=t14:13:14 if you are not in China ecosystem

I would love to have TD_5.0.1_Win7_64bit_NL

Any Chinese Friend can help on that ?  blueskull ?

[poleguy]

I'm new to the forums here, but I've been working as EE doing mostly FPGA designs since graduating in EE in 1999. Here's my take on the FPGA industry from that perspective.

At this point it seems the two big players, Altera and Xilinx are primarily driven by a growth strategy that's focused on truly massive designs and on datacenter applications. This leaves the new huge FPGA parts out of reach for the little guys (individuals or even companies trying to put them into products at consumer price points.) Unfortunately this means that there is little innovative development on small, low power, or even moderately sized designs from A or X.

It seems the datacenter designs are focused mainly on high level synthesis, so that the "FPGA" designers don't actually need to know how to produce an efficient FPGA design and rather can build a high level model and let the tools 'make it fast.' They may be 50% inefficient, but in the right markets that's not really a problem. The efficient low-level FPGA designer is becoming like a COBOL designer: obsolete, but highly valuable in a very small niche.

Even the designers who work with relatively big parts tend to do most of their work piecing together IP blocks purchased from X or A, or even free from X or A, which trades fast results for a bit of vendor-lock-in. This makes you very tied to the vendor, to the tools, the part family, and even to the tool version. For a moderately sized company seeking rapid ship dates and maximal profit for minimal up-front design cost, this sort-of makes sense, but those designs are going to end-up leaving designers with long term technical-debt (design-for-maintenance?).

Recently we had a case where Xilinx introduced (and eventually fixed) a bug in its VHDL synthesizer that caused x + 1 to be evaluated to x - 1 in certain hard to determine cases. This shows that the flow they are using is likely only really tested on high-level-synthesized designs, so there is ongoing risk that synthesis of hand coded designs may be at risk for synthesis changes that break legacy designs. It seems likely that Verilog and SystemVerilog are getting tested more extensively than VHDL because the high level languages use that by default. Xilinx won't admit this. At the moment they promise HDL won't go away, but it seems a risk that they may change there mind later and have HDL just become practically unusable because the tools aren't designed around that use case, or that they might introduce a high-level-synthesis only flow where all the new features go. (I'm speculating of course.)

Here around Chicago there are some jobs building high-frequency-trading systems for the guys who like to gamble with other people's money, and there are some defense jobs, and a well known microphone company, and the shell pieces of dying motorola. Otherwise you'll need to move (or zoom maybe) to Texas, etc. where the tech industry is hotter.

Some other parts smaller players like lattice provide some nice parts that are small cheap and simple. It's now the case that any logic beyond single gate transistors makes sense to be in a small FPGA. The cheap FIFO chip that peter-h mentions above is no longer cheap or available at all. I have on my bench in front of me now a design with a Xilinx Artix 7 that interfaces serially with a small lattice part on another board that is used to break out 40 GPIO. This greatly simplifies the board to board connection, and at this point serial to parallel shift registers (e.g. 74*595) end up more expensive. 

The transceivers in these designs allow for simple and cheap fiber-optic links even, and it's still a fun time to be working in the industry, but it seems the interesting jobs are few and less interesting than in the past.

Nick

[0db]

recently we had a case where Xilinx introduced (and eventually fixed) a bug in its VHDL synthesizer that caused x + 1 to be evaluated to x - 1 in certain hard to determine cases.

with which software (ISE? Vivado?) and version and for which target device (spartan3,6,7, ... others)?

[AndyC_772]

I'd agree with a lot of that, the big players' focus on data centre applications to the exclusion of all 'small' parts is obvious, and harmful.

One of my all-time favourite ICs is the smallest Cyclone IV part from Altera, the EP4CE6E22. It has a quantity of logic and memory that's a good fit for a number of projects, and way more I/O than I often need. I wish it came in 64 or 100 pin packages.

I also wish it wasn't 11 years old already, not as horrendously costly for what you get, and that the newer Cyclone 10LP was significantly better in any way. Put it on a BoM with a modern microcontroller and the lack of development progress in the last 10 years on the FPGA side is painful.

I don't mind the vendor lock-in. My board is designed to use a whole bunch of sole-source components; I'm not going to change CPU manufacturer without a very good reason, nor am I inclined to change even relatively generic analogue parts in designs that have been thoroughly tested, qualified and field-proven over many years. Any suggestion that I'm somehow storing myself up a future problem by instantiating an Altera memory function or multiplier is missing the point by a country mile.