What FPGA boards can receive/send data to PC through USB?

[caspian]

Dear members,

I need a FPGA board that can be connected to a PC using USB. I need to send the input data of the FPGA chip through USB from a PC to the inputs of the Chip and then, receive the output data of the FPGA chip through USB from the outputs of the FPGA chip to the PC.

Does a FPGA board such as Mojo v3 have this capability?
If not so, what FPGA boards do have this capability to receive/send data through USB?

Is there any tutorial that clarifies how to use this capability?

Thanks


note1: I do not mean to receive/send the FPGA Chip's program through USB.
note2: I do not want to use a PCIe FPGA board.

[langwadt]

did you try google?

https://alchitry.com/hello-world-verilog

[pcprogrammer]

There are lots of FPGA boards that have simple USB to serial converters like CH340 on it. Easy to interface on the FPGA but data rate is limited to ~2Mbits per second. When you need more then that you have to look into other solutions.

Boards that I have some experience with come from:

PiSwords has Xilinx and Altera based boards, but prices went up like crazy
http://piswords.com/demoboard.html
https://nl.aliexpress.com/item/32828884647.html

Another one is QMTECH but there you need either a daughter board plus a FPGA board to get the USB interface, or a more expensive board with it all on one board.
https://qmtechchina.aliexpress.com/store/4486047

You can also get some CH340 or similar USB to serial modules and connect them to a cheaper FPGA board that does not have such an interface on it.

[Berni]

The usual is indeed USB to UART bridges. They are really easy to implement, but as others have said they can only do up to 1 to 5 Mbit/s

If you want more speed then things get a bit more complicated. One way is using Ethernet to get 1Gbit/s. You can just send raw MAC address traffic to sidestep needing a whole TCP/IP stack and such, but even that is quite a bit of work. Directly doing USB HS on a FPGA to get 480Mbit/s is possible but also quite complex.

A nice cheat for getting high speed is the  FT600 chip from FTDI that gives you a USB 3.0 to 16/32bit parallel bus bridge at about 3Gbit/s. This makes it really easy to interface to a FPGA since you just set the data pins and clock it in. The FTDI chip takes care of buffering it and sending it over while on the PC side the driver looks much like a serial port (Whatever you send into the bus you get as a sequence of bytes on the PC)

[pcprogrammer]

A nice cheat for getting high speed is the  FT600 chip from FTDI that gives you a USB 3.0 to 16/32bit parallel bus bridge at about 3Gbit/s. This makes it really easy to interface to a FPGA since you just set the data pins and clock it in. The FTDI chip takes care of buffering it and sending it over while on the PC side the driver looks much like a serial port (Whatever you send into the bus you get as a sequence of bytes on the PC)

A nice solution but not that cheap. But FTDI has a wide range of devices to choose from that might fit the bill for a lower price.

Another slightly more complicated and only USB2.0 (480Mbits/s) is using an MCU like the F1C100s as an interface between the FPGA and the PC. This gives you full control on the communication between the two devices but involves writing drivers.

[caspian]

In the Mojo v3 board, if some data is received by the Spartan6 chip from the serial port, what section of the chip do the data enters?
the internal RAM? or a specific block?

Can I program the Spartan6 chip so that the serially-received data enter all the logic blocks of the chip for processing?
Are the logic blocks that the serially-received data can enter for processing, limited to a few blocks?

Is there any limitation (other than data rate) on processing of serially-received data compared to parallel-received data that enter the chip from the IO pins?

[pcprogrammer]

I'm not familiar with the Mojo v3 board, but the way a FPGA works is that you make the programming for it. When an USB to serial module is connected to the FPGA it most likely uses only the RX and the TX lines. In the FPGA you have to connect these signals to your logic. There is no dedicated serial interface on a FPGA (apart from JTAG and configuration logic)

Look for verilog or VHDL uart examples. These will provide you with parallel data buses for incoming and outgoing data. Connect these to the rest of your logic in the FPGA.

After converting the serial data to parallel with one of those uart examples it is just the same as having parallel IO lines connected to the FPGA.

All you have to be aware of is clock domains. Make sure that you synchronize to your main clock in a correct way, and preferably only use one main clock if possible.

[pcprogrammer]

I looked at the schematic of the Mojo v3 and noticed that it uses the ATMEGA32 as a possible USB to serial bridge. This means you have to write code for the MCU to handle the communication between the PC and the FPGA.

This also allows you to do a parallel interface on the FPGA since a lot of the GPIO pins of the ATMEGA32 are connected to the FPGA.

Just take a good look at the schematic on how things are connected: https://cdn.sparkfun.com/datasheets/Dev/FPGA/mojov3-sch.pdf

[langwadt]

I looked at the schematic of the Mojo v3 and noticed that it uses the ATMEGA32 as a possible USB to serial bridge. This means you have to write code for the MCU to handle the communication between the PC and the FPGA.

no, the ATMEGA32 comes programmed to configure the fpga, act as serial to usb bridge and supply adc data to the fpga if needed

[langwadt]

In the Mojo v3 board, if some data is received by the Spartan6 chip from the serial port, what section of the chip do the data enters?
the internal RAM? or a specific block?

Can I program the Spartan6 chip so that the serially-received data enter all the logic blocks of the chip for processing?
Are the logic blocks that the serially-received data can enter for processing, limited to a few blocks?

Is there any limitation (other than data rate) on processing of serially-received data compared to parallel-received data that enter the chip from the IO pins?

I think you need to take a few steps back and start at the beginning, first step is understanding what an fpga is.

[Berni]

In the Mojo v3 board, if some data is received by the Spartan6 chip from the serial port, what section of the chip do the data enters?
the internal RAM? or a specific block?

Looks like you first need to learn about what FPGAs are and how to use them.

They do not work like a MCU where they have predefined interfaces and data paths, no big RAM area that you can just read/write to in any way you want. The FPGA is mostly just a giant pile of logic gates that get wired together to perform a function. Sending data into a FPGA is just wiggling a IO pin, it is then your job to build logic inside that interprets that wiggling as the data you want to receive. This is the main benefit of FPGAs, they can implement any interface you want without needing dedicated hardware for it.

[pcprogrammer]

no, the ATMEGA32 comes programmed to configure the fpga, act as serial to usb bridge and supply adc data to the fpga if needed

Is it not possible to reprogram the ATMEGA32?

Sure you have to write the code to load the FPGA, but that should not be to hard. Either serial bit banging or writing parallel bytes to it. The pins can be reused to interface between the ATMEGA32 and the FPGA.

I think you need to take a few steps back and start at the beginning, first step is understanding what an fpga is.

But I agree that it looks like caspian has to start from the beginning and learn how to use the FPGA first.

[DiTBho]

Code: [Select]

     FPGA    |
             |
             |
splitter     |                                              _____
  |          |                                             |     |
  +--- fifo0 |===== serial0 5Mbps ===== serial-to-usb =====|     |
  +--- fifo1 |===== serial1 5Mbps ===== serial-to-usb =====| USB |===== 20Mbps ==== bonding
  +--- fifo2 |===== serial2 5Mbps ===== serial-to-usb =====| HUB |
  +--- fifo3 |===== serial3 5Mbps ===== serial-to-usb =====|     |
             |                                             |_____|

this would be insanely great (did I say "insanely"? ) 

crazy 

[Foxxz]

I have used a mojo board. There are serial examples in verilog for it. It's a decent board but it was difficult for a beginner to get started with it. I would suggest finding a book for beginners that teaches about using a specific board and then buying that board to follow along with the book.

But to echo what others have said an FPGA isn't magic and you have to do alot of work to get it to do something. An FPGA doesn't understand what serial or USB is. You have to write code that describes the protocol down to the binary level and how to interact with it. You can make the data you send and receive work however you want such as loading it into a block ram or passing it to another module within the FPGA.

There are often examples and 'cores' others have written you can use but unless they are for the specific board you are using you will still need to do some work to make them usable. Even then they make not work how you envision or need them to function.

[SiliconWizard]

The only dev board that I know of that has a FT2232H with enough IOs connected to the FPGA so that it can be used in parallel mode (albeit only asynchronous, because AFAIR, the clock out is not routed) is the Numato Saturn: https://numato.com/product/saturn-spartan-6-fpga-development-board-with-ddr-sdram/
I've used it successfully in the asynchronous parallel mode.

The async FIFO mode of the FT2232H allows throughputs of up to about 8MBytes/s. Not nearly as much as you can get with the synchronous mode, but way higher than anything you could get with a USB to serial interface.

For the record, it's interesting to note that, while many FPGA dev boards include the FT2232H chip (because it can be used as a JTAG interface very easily), most of them only route the second channel as a UART interface, while routing a few more IOs would allow the async (or better yet, the sync) parallel mode. Of course, you can always quickly add this kind of interface using a FT2232H breakout board and connecting it to your FPGA board (keep connections short for parallel modes.)

[free_electron]

A nice cheat for getting high speed is the  FT600 chip from FTDI that gives you a USB 3.0 to 16/32bit parallel bus bridge at about 3Gbit/s. This makes it really easy to interface to a FPGA since you just set the data pins and clock it in. The FTDI chip takes care of buffering it and sending it over while on the PC side the driver looks much like a serial port (Whatever you send into the bus you get as a sequence of bytes on the PC)

this !. you can do the same with the 4232 or certain 2232 chips as well. they emulate a 8051 bus interface (16 bit address, 8 bit data, read and write strobe and give you a couple of handshake lines.
all you do on the fpga side is implement a DPRAM.

I typically work that way. simply map the register in the FPGA as a virtual ram and the pc can read/write anything it wants. no need for doing complicated uart emulation, fifos and converting stuff to from ascii. you have a channel directly from the PC side to the flipflops.
you get 65536 8-bit registers that are random access. if you need more: bank them. use the top byte as index and you can make 256 banks of 65535 ... you'll exhaust the FPGA trying to read/write 134 million bits.

[langwadt]

The only dev board that I know of that has a FT2232H with enough IOs connected to the FPGA so that it can be used in parallel mode (albeit only asynchronous, because AFAIR, the clock out is not routed) is the Numato Saturn: https://numato.com/product/saturn-spartan-6-fpga-development-board-with-ddr-sdram/
I've used it successfully in the asynchronous parallel mode.

The async FIFO mode of the FT2232H allows throughputs of up to about 8MBytes/s. Not nearly as much as you can get with the synchronous mode, but way higher than anything you could get with a USB to serial interface.

For the record, it's interesting to note that, while many FPGA dev boards include the FT2232H chip (because it can be used as a JTAG interface very easily), most of them only route the second channel as a UART interface, while routing a few more IOs would allow the async (or better yet, the sync) parallel mode. Of course, you can always quickly add this kind of interface using a FT2232H breakout board and connecting it to your FPGA board (keep connections short for parallel modes.)

I've used this one https://numato.com/product/mimas-a7-artix-7-fpga-development-board/

afair close to 40MBytes/s in sync FIFO mode

[DiTBho]

afair close to 40MBytes/s in sync FIFO mode

is there any code example?

[free_electron]

i believe ftdi or altera or terasic have sample code. i rolled my. i know ftdi has it for the ftd6xx

[chickenHeadKnob]

Cypress (now Infineon I think) FX2 boards that you can still  buy cheap on aliexpress have USB2 high speed to parallel throughput similar to FTDI2232H. They have an internal 8051. You can find open source drivers for them, in particular the author of the sigrok drivers has an excellent but moribund youtube channel "OpenTechLab". He describes programming these board(s) in two of his videos. Boards plural to denote the generic FX2 board or the salae logic clone board.

[mblinov]

This is one of the major reasons i've been looking into Gowin FPGAs. USB 2.0 PHY right on the chip, plus royalty free IP for it.

still though, you have to hook it up yourself - still figuring out whether theres some EHCI wrapper to make it easy to inter-operate with for example TinyUSB.

Gowin have an entire video on this - there is some usb 3.0 stuff on the horizon too, which i think is quite exciting.

[langwadt]

afair close to 40MBytes/s in sync FIFO mode

is there any code example?

I think numato might have some, else there is several on github that isn't board specific

[langwadt]

This is one of the major reasons i've been looking into Gowin FPGAs. USB 2.0 PHY right on the chip, plus royalty free IP for it.

the advantage with the FT2232 is that it has drivers and you can swap between jtag and fifo so you can use it for both communication and configuration

[DiTBho]

Thanks guys 

-

Actually, I have already implemented the crazy  four serials in bonding mode, with four FIFO buffers and a fsm to manage them.

Many years ago, when Giga-Ethernet was very expensive, we used a couple of Digital Tulip quad Fast-Ethernet PCI-X cards in that bonding setup.

Code: [Select]

computerA     |                              |    computerB
              |                              |
 Kernel Linux |                              | kernel Linux
  bonding net |           TCP/IP             |  bonding net
   PCI-X      |        142Mbyte/sec          |   PCI-X
    QuadTulip |                              |    QuadTulip
        +----ch0 ===== ethernet cable ===== ch0 ----+
        +----ch1 ===== ethernet cable ===== ch1 ----+
        +----ch2 ===== ethernet cable ===== ch2 ----+
        +----ch3 ===== ethernet cable ===== ch3 ----+
              |                              |
______________|                              |_______________

it was possible to move up to 142Mbyte/sec over four ethernet cables. Shocking these days even a 30 euro RPI can do it better and cheaper 


That's why I implemented the quad-serial bonding thing. Nostalgia ...

[Bassman59]

For the record, it's interesting to note that, while many FPGA dev boards include the FT2232H chip (because it can be used as a JTAG interface very easily), most of them only route the second channel as a UART interface, while routing a few more IOs would allow the async (or better yet, the sync) parallel mode. Of course, you can always quickly add this kind of interface using a FT2232H breakout board and connecting it to your FPGA board (keep connections short for parallel modes.)

I wonder if they don't wire it up for the parallel mode because that requires host driver support, as it needs to conform to some Vendor-Specific class and not a standard Class? That means host software, too.