Electronics > FPGA

What has happened to my Vivado Project?

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Mario87:
Hi all,

I opened Vivado and made some changes to the block design of my project, but when I went to re-synthesize I keep getting the error message below saying one of the IP dcp files doesn't exist, but when you look at the file location it is nonsense.

The file does exist, I have found it as part of the out of context synthesis in its own folder, but for some reason Vivado keeps looking for it in the location below. Anyone know how I can correct this and point vivado to the right location??


--- Quote ---[Runs 36-527] DCP does not exist: C:/PROJECT/PROJECT.runs/synth_1/Users/MyName/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-21428-MyName-PC/coregen/video_processing_mig_7series_0_0/video_processing_mig_7series_0_0.dcp

--- End quote ---

The correct file location should be C:/PROJECT/PROJECT.gen/sources_1/bd/video_processing/ip/video_processing_mig_7series_0_0/video_processing_mig_7series_0_0.dcp

Any help greatly appreciated as I really don't want to have to re-create the project!

Mario87:
Anyone any ideas? I have found that if I reset the synth run, make the C:/PROJECT/PROJECT.runs/synth_1/Users/MyName/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-21428-MyName-PC/coregen directory and then copy the video_processing_mig_7series_0_0 directory from the correct location into this new directory then run synthesis, it works totally fine.

The issue is that every time I run synthesis it deletes everything in the synth_1 folder and I have to re-create the folder structure.

So the project appears to be "fine", just that vivado is pointing in the wrong place for these file locations.
 
Surely there must be some way to fix this / change the location vivado is checking....but how do I do that?

Someone:
Vivado projects are brittle, the UI hides what is going on. Its pretty common to have projects fall apart like this where the underlying tools spit out errors but there is no obvious way in the GUI to influence what they are complaining about. Most errors with block diagrams are fixed by resetting the design, manually deleting all the cached/intermediate build products, and regenerating them all from scratch. Move to a non-project flow to save time.

Mario87:
Just for info, I managed to work around this by deleting the MIG7 IP block and creating a new one that has "_1" at the end instead of "_0". Project now synthesis' without that silly error.

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