Author Topic: What HDL to start with  (Read 16133 times)

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Offline tggzzz

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Re: What HDL to start with
« Reply #125 on: April 12, 2020, 10:43:04 am »
There's also nothing stopping anyone from leaning multiple languages,
I'd be careful with this advice. It takes a really long time to learn how to use a programming language effectively. It is not only the syntax but also the libraries which come with it (or a set of vendor specific libraries). As I wrote before: I have invested quite a bit of time to learn the more advanced constructs of VHDL which makes me work very effectively with it. If I had to do the same with Systemverilog I'd be learning a different language with the same goal. That isn't very efficient use of time. BTW you can swap the language names and my claim is still true.

@tggzz: Lotus123 is a spreadsheet; not a word processor

Shrug. I couldn't remember the name of the MSOffice spreadsheet component.

Quote
and VHDL most certainly isn't equal to Verilog. There is too much missing from Verilog as a programming language to make a meaningful comparison to VHDL. VHDL compares to Verilog like C compares to assembler.

You miss the point. An, any, HDL is radically different from a spreadsheet or an HLL. By comparison the differences between HDLs is minor.

Ditto between HDLs and analogue simulators or symbolic algebra languages.

In a similar vein, all screwdrivers are pretty much the same when compared with hammers.

It is necessary to know when to use a hammer and when to use a screwdriver. If you can use one screwdriver, you can quickly learn to use another.
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Online nctnico

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Re: What HDL to start with
« Reply #126 on: April 12, 2020, 11:10:18 am »
It is necessary to know when to use a hammer and when to use a screwdriver. If you can use one screwdriver, you can quickly learn to use another.
Unfortunately your screwdriver analogy doesn't work for programming languages. Sure if you know how to use GCC you can use a different C compiler as well. But to say that -for example- if you know how to program in Pascal you can pick up C easely is just wrong. A programming language goes far beyond just the syntax. The ecosystem around it also comes into play.
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Offline SiliconWizard

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Re: What HDL to start with
« Reply #127 on: April 12, 2020, 03:50:32 pm »
There is too much missing from Verilog as a programming language to make a meaningful comparison to VHDL. VHDL compares to Verilog like C compares to assembler.
Unfortunately (to me) I think that vendors are more inclined to support SV than VHDL.

What a weird assumption. What would make you think that?
Whereas I have no hard figures (they are hard to find), my small humble research tended to show me that VHDL was more widespread than Verilog worldwide actually. I can't provide hard proof of that though.

But whatever, VHDL has been around (and supported) for much longer than SV, there are still much fewer tools supporting SV than VHDL.

As we discussed earlier in the thread, if you specifically think that vendors tend to lag in supporting VHDL-2008 and later, that is true, but they tend to lag in supporting SV as well. And as I said, VHDL even with older std versions (such as 2002) is perfectly usable. There's a much narrower gap between VHDL-2002 and 2008 than between Verilog and SV.

And whereas VHDL still tends to be favored for safety-critical designs, I think it has nice days ahead.
I'm absolutely not worried about it.
 

Offline TomS_

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Re: What HDL to start with
« Reply #128 on: April 19, 2020, 08:01:36 am »
I've just started playing with some CPLDs and decided to go with Verilog after watching some videos and reading examples for both.

For me, the Verilog syntax looked and felt better to write than VHDL.

I'm happy with my choice, but I don't have the experience to know whether I've made the "right" choice.

So far I'm feeling productive and achieving what I need to achieve, but I've got a pretty good ability for picking up new languages, so if this doesn't happen to work out for some reason I'm not that worried.
 

Offline tggzzz

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Re: What HDL to start with
« Reply #129 on: April 19, 2020, 08:23:43 am »
I've just started playing with some CPLDs and decided to go with Verilog after watching some videos and reading examples for both.

For me, the Verilog syntax looked and felt better to write than VHDL.

I'm happy with my choice, but I don't have the experience to know whether I've made the "right" choice.

So far I'm feeling productive and achieving what I need to achieve, but I've got a pretty good ability for picking up new languages, so if this doesn't happen to work out for some reason I'm not that worried.

I suggest that, for any language, the syntax is much less important than the semantics.

I'm less interested in whether I can "express things right", more interested in whether I can "express the right things".
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
Having fun doing more, with less
 


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