There is too much missing from Verilog as a programming language to make a meaningful comparison to VHDL. VHDL compares to Verilog like C compares to assembler.
Unfortunately (to me) I think that vendors are more inclined to support SV than VHDL.
What a weird assumption. What would make you think that?
Whereas I have no hard figures (they are hard to find), my small humble research tended to show me that VHDL was more widespread than Verilog worldwide actually. I can't provide hard proof of that though.
But whatever, VHDL has been around (and supported) for much longer than SV, there are still much fewer tools supporting SV than VHDL.
As we discussed earlier in the thread, if you specifically think that vendors tend to lag in supporting VHDL-2008 and later, that is true, but they tend to lag in supporting SV as well. And as I said, VHDL even with older std versions (such as 2002) is perfectly usable. There's a much narrower gap between VHDL-2002 and 2008 than between Verilog and SV.
And whereas VHDL still tends to be favored for safety-critical designs, I think it has nice days ahead.
I'm absolutely not worried about it.