Electronics > FPGA

What is the standard procedure to design the power delivery network?

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miken:
Many designs out there don't have severe requirements, so often any sort of "good enough" design will work. There's a lot of wiggle room for personal preference: some people like to use integrated power modules, some people like to make things as difficult for themselves as possible, some stick to what they know. If you have other design constraints (cost, power, space, hi-speed) then it gets more interesting.

And then it's possible that your baseline FPGA project works fine on your HW but then an upgraded project doesn't, as you attempt to cram more stuff in ;D So there can be a bit of predicting the future involved.

matrixofdynamism:
I have even seen a CPLD being used as power up sequencer on an FPGA board like Cyclone series board have Max II or Max V CPLD doing the power up sequencing.

Anyway. If I want to learn in detail about this subject, what search term should I use on Google? Also, what application notes or books can I be use?

It does seem that there is a lot to learn on this subject and I know very little.

tom66:
The technical reference manual (TRM) for your particular FPGA family is always a good place to start.

If you can find a reference implementation schematic for a dev kit that's useful.  I based the oscilloscope project I made on the MYiR Z-turn Lite dev kit initially, then when I spun my own board I used it as inspiration for the design.  I had to reduce it to x16 DDR3 instead of x32 because of space/routing constraints (and I wasn't brave enough to go for a split address bus on one of my first high-density boards.)

I've also heard good things from FEDEVEL Academy, but that's a paid course so up to you if you want to do it.

SiliconWizard:

--- Quote from: matrixofdynamism on June 23, 2022, 09:00:51 am ---I have even seen a CPLD being used as power up sequencer on an FPGA board like Cyclone series board have Max II or Max V CPLD doing the power up sequencing.

--- End quote ---

Sure. As I mentioned, there are dedicated ICs for power sequencing. Lattice has some, and those are essentially glorified CPLDs. For instance:
https://www.latticesemi.com/en/Products/PowerAndClockDevices/PowerManager

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