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What is the standard procedure to design the power delivery network?

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FPGAs and ASICs take a large number of voltage rails that need to be turned on in specific sequence. A complex board will thus have a large number of power supply rails for the FPGA and the other components like ADC, DAC, MCU, Ethernet PHY e.t.c.

There are a variety of ICs that can be used to generate the voltage rails. These are linear voltage regulators, DC-DC switched mode converters. Some of them need no extermal components at all, some need a few external components while many need a lot of external components.

If I am designing a board and know what voltage rails I need, their sequence, and the current draw on each of them, how would I go about designing the entire power delivery system? I never learnt about how to do this in university. Are there any application notes on this? Any help is appreciated!

The major FPGA suppliers have been producing volumes of detailed application notes, complete with theory and examples. A modern example might be:
XAPP1375 Versal ACAP Simplified Power Sequencing
going back through older devices can find other approaches

There also are dedicated power sequencing ICs out there.

Most of your voltage regulators have an enable line and you can chain the voltage output of one regulator to the enable of the next regulator in the chain. It works pretty well for basic cases.

The way I approach it is as follows (I work mostly with Xilinx devices, but I'm sure other vendors provide similar tools):
1. Once I settle to a device I'm going to use, I take XPE (Xilinx Power Estimator Excel spreadsheet) and set up artificially high utilization to figure out the worst case power consumption.
2. Depending on the design, I select components for DC-DC converters. If the board needs to be as compact as possible, I use power modules with integrated inductors as they are the most space-efficient. If cost is a concern, I settle for DC-DC bucks with external inductors (it's usually cheaper). For each design, once current demands for each rail are determined, I typically select parts as to have some margin as far as current is concerned.
3. In either case, I give priority to parts I worked with in the past. For parts new to me, I always build a small 4-layer prototype and characterize it to make sure it meets all requirements for power regulation like ripple voltage and regulation accuracy. FPGAs require rather clean and precise power supplies, with ±3% being rather common, and <50 mVpp ripple, so that step is important to verify in practice rather than in simulation, because unsufficiently clean rails can cause some weird problems with device in the future.
4. If the PDS contains any new (to me) parts, I only assemble PDS-related components on the very first PCB so that I can verify PDS once again before I install expensive FPGA. This is my last line of defence against PDS issues destroying some expensive components. I also typically load up all rails to see if there are any thermal issues.
5. Since thermal regime is often a concern in my designs, I use switching DC-DC converters wherever I can, and when I have to use LDOs, I use a switching DC-DC pre-regulator paired to a split-rail LDO with dedicated bias input (like TI's TPS74901 or TPS7A92). This approach allows for minimal dropout voltage and higher efficiency and lower heat dissipation. This is a typical solutiuon for sensitive analog power rails like transceivers power, PLLs, ADCs and other when clean power is an overriding concern.
6. Modern FPGAs require very fast transient response, so DC converters needs to be placed as close as possible to the consumers, and not relegated to a single corner like some people like to do. This also helps with thermal regime because it spreads heat-generating components across the board.

Now, I haven't had a chance to work with some really high-power FPGAs, the most power-hungry one I worked with requires about 30 Amps of current, so no 100+ Amps rails, for those you will need to pay attention to your power planelets to make sure they can actually carry enough current to FPGA power balls considering all perforations caused by a via field. Somewhere in Xilinx docs I remember some "rules of thumb" regarding this problem, but like I said, it hasn't been a problem for me yet. But in this case you will need to add additional PCB layers to add more power planelets.

Also, Xilinx recently has released an appnote XAPP1375, which is very relevant to this discussion, so you might want to read it even if you are planning to use other vendor's devices.


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