Author Topic: What is the standard procedure to design the power delivery network?  (Read 737 times)

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Offline matrixofdynamism

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FPGAs and ASICs take a large number of voltage rails that need to be turned on in specific sequence. A complex board will thus have a large number of power supply rails for the FPGA and the other components like ADC, DAC, MCU, Ethernet PHY e.t.c.

There are a variety of ICs that can be used to generate the voltage rails. These are linear voltage regulators, DC-DC switched mode converters. Some of them need no extermal components at all, some need a few external components while many need a lot of external components.

If I am designing a board and know what voltage rails I need, their sequence, and the current draw on each of them, how would I go about designing the entire power delivery system? I never learnt about how to do this in university. Are there any application notes on this? Any help is appreciated!
 

Online Someone

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Re: What is the standard procedure to design the power delivery network?
« Reply #1 on: June 22, 2022, 12:36:17 am »
The major FPGA suppliers have been producing volumes of detailed application notes, complete with theory and examples. A modern example might be:
XAPP1375 Versal ACAP Simplified Power Sequencing
going back through older devices can find other approaches
 

Offline SiliconWizard

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Re: What is the standard procedure to design the power delivery network?
« Reply #2 on: June 22, 2022, 01:17:31 am »
There also are dedicated power sequencing ICs out there.
 

Offline Foxxz

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Re: What is the standard procedure to design the power delivery network?
« Reply #3 on: June 22, 2022, 01:24:23 am »
Most of your voltage regulators have an enable line and you can chain the voltage output of one regulator to the enable of the next regulator in the chain. It works pretty well for basic cases.
 

Offline asmi

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Re: What is the standard procedure to design the power delivery network?
« Reply #4 on: June 22, 2022, 03:10:41 am »
The way I approach it is as follows (I work mostly with Xilinx devices, but I'm sure other vendors provide similar tools):
1. Once I settle to a device I'm going to use, I take XPE (Xilinx Power Estimator Excel spreadsheet) and set up artificially high utilization to figure out the worst case power consumption.
2. Depending on the design, I select components for DC-DC converters. If the board needs to be as compact as possible, I use power modules with integrated inductors as they are the most space-efficient. If cost is a concern, I settle for DC-DC bucks with external inductors (it's usually cheaper). For each design, once current demands for each rail are determined, I typically select parts as to have some margin as far as current is concerned.
3. In either case, I give priority to parts I worked with in the past. For parts new to me, I always build a small 4-layer prototype and characterize it to make sure it meets all requirements for power regulation like ripple voltage and regulation accuracy. FPGAs require rather clean and precise power supplies, with ±3% being rather common, and <50 mVpp ripple, so that step is important to verify in practice rather than in simulation, because unsufficiently clean rails can cause some weird problems with device in the future.
4. If the PDS contains any new (to me) parts, I only assemble PDS-related components on the very first PCB so that I can verify PDS once again before I install expensive FPGA. This is my last line of defence against PDS issues destroying some expensive components. I also typically load up all rails to see if there are any thermal issues.
5. Since thermal regime is often a concern in my designs, I use switching DC-DC converters wherever I can, and when I have to use LDOs, I use a switching DC-DC pre-regulator paired to a split-rail LDO with dedicated bias input (like TI's TPS74901 or TPS7A92). This approach allows for minimal dropout voltage and higher efficiency and lower heat dissipation. This is a typical solutiuon for sensitive analog power rails like transceivers power, PLLs, ADCs and other when clean power is an overriding concern.
6. Modern FPGAs require very fast transient response, so DC converters needs to be placed as close as possible to the consumers, and not relegated to a single corner like some people like to do. This also helps with thermal regime because it spreads heat-generating components across the board.

Now, I haven't had a chance to work with some really high-power FPGAs, the most power-hungry one I worked with requires about 30 Amps of current, so no 100+ Amps rails, for those you will need to pay attention to your power planelets to make sure they can actually carry enough current to FPGA power balls considering all perforations caused by a via field. Somewhere in Xilinx docs I remember some "rules of thumb" regarding this problem, but like I said, it hasn't been a problem for me yet. But in this case you will need to add additional PCB layers to add more power planelets.

Also, Xilinx recently has released an appnote XAPP1375, which is very relevant to this discussion, so you might want to read it even if you are planning to use other vendor's devices.
« Last Edit: June 22, 2022, 05:59:01 am by asmi »
 
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Offline jrx07

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Re: What is the standard procedure to design the power delivery network?
« Reply #5 on: June 22, 2022, 09:21:52 am »
Thanks for sharing your approach asmi.

What's the benefit of using an LDO with dedicated biasing?
 

Offline matrixofdynamism

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Re: What is the standard procedure to design the power delivery network?
« Reply #6 on: June 22, 2022, 01:30:03 pm »
Thanks for that answer asmi.

When I looked at schematics of different FPGA boards, I found that some use only linear voltage regulators, some use switched mode power supply ICs, some used a mixture of these, some voltage regulators used external FETs while others did not some did not, some used a lot of external components while others used few external components. I also came across a board that used ready-made voltage regulation module that came as a a small prebuilt PCB with pads and was just soldered onto the FPGA board.

The number of variations I came across was just mind boggling and did not make sense. This raised the question for me, how do those engineers know what components to use? There is of course a lot of different ICs that do basically the same thing so I am not referring to that. I am talking about the differences I observed that are mentioned in the paragraph above.
 

Offline asmi

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Re: What is the standard procedure to design the power delivery network?
« Reply #7 on: June 22, 2022, 02:36:20 pm »
What's the benefit of using an LDO with dedicated biasing?
As I said above, they allow for much lower dropout voltage, and so higher efficiency and lower heat dissipation. For LDOs, input current essentially equals to output current, and so the power dissipation is Vdrop * I, in case of a typical non-biased LDO having Vdrop at around 1 V at 2 Amps, while typical biased one can have Vdrop as low as 0.3 V, or even lower in some cases (for example, abovementioned TPS74901 has Vdrop of only 0.28 V max at 3 Amps over entire PVT!), so you can have 70% lower power dissipation (1 V * 3 Amps = 3 W for regular LDO vs 0.28 * 3 Amps = 0.84 W), which is a big deal if you have several of those on a relatively small PCB.

Offline asmi

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Re: What is the standard procedure to design the power delivery network?
« Reply #8 on: June 22, 2022, 02:50:21 pm »
The number of variations I came across was just mind boggling and did not make sense. This raised the question for me, how do those engineers know what components to use? There is of course a lot of different ICs that do basically the same thing so I am not referring to that. I am talking about the differences I observed that are mentioned in the paragraph above.

Well I don't know how others do it (unless they come out and tell us), so I'm sharing how I do it, which is something I do know :) I would hazard a guess it's a typical conundrum of availability vs solution cost (not just the main IC, but with supporting components) vs PCB area (space on a multi-layer PCB is expensive, so there is an incentive to go for more compact solutions, also more compact designs tend to provide for a better end product - smaller, ligher, cheaper enclosure, etc.) vs familiarity (this affects R&D costs, unfamiliar parts require additional R&D to figure out optimal solutions, prototype and characterize them to confirm suitability).

Offline tom66

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Re: What is the standard procedure to design the power delivery network?
« Reply #9 on: June 22, 2022, 02:51:16 pm »
On all the boards I've designed with an FPGA, I've always used a little microcontroller to handle the job.  It just enables each power supply, checking PG if necessary.  It also handles reverse sequencing and brown out detection for the power supply, usually batteries.

Why?  Low effort, I can reprogram it when I need if I screw up the sequencing.  It usually does some other important interface task, so may as well use it to glue other things together. 
 

Offline miken

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Re: What is the standard procedure to design the power delivery network?
« Reply #10 on: June 23, 2022, 05:58:00 am »
Many designs out there don't have severe requirements, so often any sort of "good enough" design will work. There's a lot of wiggle room for personal preference: some people like to use integrated power modules, some people like to make things as difficult for themselves as possible, some stick to what they know. If you have other design constraints (cost, power, space, hi-speed) then it gets more interesting.

And then it's possible that your baseline FPGA project works fine on your HW but then an upgraded project doesn't, as you attempt to cram more stuff in ;D So there can be a bit of predicting the future involved.
 

Offline matrixofdynamism

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Re: What is the standard procedure to design the power delivery network?
« Reply #11 on: June 23, 2022, 09:00:51 am »
I have even seen a CPLD being used as power up sequencer on an FPGA board like Cyclone series board have Max II or Max V CPLD doing the power up sequencing.

Anyway. If I want to learn in detail about this subject, what search term should I use on Google? Also, what application notes or books can I be use?

It does seem that there is a lot to learn on this subject and I know very little.
 

Offline tom66

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Re: What is the standard procedure to design the power delivery network?
« Reply #12 on: June 23, 2022, 10:35:57 am »
The technical reference manual (TRM) for your particular FPGA family is always a good place to start.

If you can find a reference implementation schematic for a dev kit that's useful.  I based the oscilloscope project I made on the MYiR Z-turn Lite dev kit initially, then when I spun my own board I used it as inspiration for the design.  I had to reduce it to x16 DDR3 instead of x32 because of space/routing constraints (and I wasn't brave enough to go for a split address bus on one of my first high-density boards.)

I've also heard good things from FEDEVEL Academy, but that's a paid course so up to you if you want to do it.
 

Offline SiliconWizard

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Re: What is the standard procedure to design the power delivery network?
« Reply #13 on: June 23, 2022, 06:26:22 pm »
I have even seen a CPLD being used as power up sequencer on an FPGA board like Cyclone series board have Max II or Max V CPLD doing the power up sequencing.

Sure. As I mentioned, there are dedicated ICs for power sequencing. Lattice has some, and those are essentially glorified CPLDs. For instance:
https://www.latticesemi.com/en/Products/PowerAndClockDevices/PowerManager

 


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