WinCUPL multilatches, shared output

[banedon]

Hi guys

I'm currently writing a design in WinCUPL for an ATF1508 CPLD which is going to be used for glue logic for a single board computer.

Part of the design will require four 8 bit latches buried in the CPLD: One to be used for RAM bank paging, and the other three used to control aspects of how the CPLD works.
The latches will need to be written to and read by the CPU by accessing certain memory locations.

The design works fine in the simulator.

What does everyone think? Can anyone see any flaws? Also, can anyone see if there is a more efficient and faster way of doing this which I haven't thought of?

Code: [Select]

/* Inputs */

Pin  2 = PHI2;                    /* Main CPU clock (fixed pin) */
Pin = RWB;                        /* CPU read/!write signal */


/* Input/Outputs */

Pin = [D7..0];                    /* D0 to D7 data bus lines from/to the CPU */


/* --- Buried Logic --- */

pinnode = banksel;                /* Bank select flag. latch is enabled if this is set to high */
pinnode = latchSelA;              /* Register A select flag. Latch is enabled if this is set to high */
pinnode = latchSelB;              /* Register B select flag. Latch is enabled if this is set to high */
pinnode = latchSelC;              /* Register C select flag. Latch is enabled if this is set to high */

pinnode = [banklatch7..0];        /* RAM bank Latch   */
pinnode = [reglatchA7..0];        /* Register Latch A  */
pinnode = [reglatchB7..0];        /* Register Latch B  */
pinnode = [reglatchC7..0];        /* Register Latch C  */

pinnode = [outnode_BL7..0]        /* Output node for RAM bank Latch */
pinnode = [outnode_regA7..0];     /* Output node for Register A Latch */
pinnode = [outnode_regB7..0];     /* Output node for Register A Latch */
pinnode = [outnode_regC7..0];     /* Output node for Register B Latch */

/* Equations */

[banklatch7..0].L = [D7..0];
[banklatch7..0].LE = PHI2 & !RWB & banksel;
[outnode_BL7..0] = [banklatch7..0];

[reglatchA7..0].L = [D7..0];
[reglatchA7..0].LE = PHI2 & !RWB & latchSelA;
[outnode_regA7..0] = [reglatchA7..0];

[reglatchB7..0].L = [D7..0];
[reglatchB7..0].LE = PHI2 & !RWB & latchSelB;
[outnode_regB7..0] = [reglatchB7..0];

[reglatchC7..0].L = [D7..0];
[reglatchC7..0].LE = PHI2 & !RWB & latchSelC;
[outnode_regC7..0] = [reglatchC7..0];

[D7..0].OE = RWB & (latchSelA # latchSelB # latchSelC # banksel);

[D7..0] = ([outnode_regA7..0] & latchSelA) # ([outnode_regB7..0] & latchSelB) # ([outnode_regC7..0] & latchSelC) # ([outnode_BL7..0] & banksel);

Explanation:

D7 to D0 is fed into each latch
The latch in question latches the data if:
- the clock (PHI2) is high
- RWB (cpu read/write signal) is low (write mode)
- Select signal (determined by address logic elsewhere) for that latch is high.

The output of a given latch will go to a holding 'out node' for that latch, which outputs in this way:
- Each bit field in the latch's 'out-node' is AND'd with the latch's own select line. If the select line is low, then the outputs will always be zero for each bit field for that latch's 'out-node'.
This is required as the output bit fields from the 'out-nodes' are OR'd together and sent to D7 to D0 pins. This process prevents the outputs of the latches affecting each other, but also guarantees that the ones which aren't enabled for outputs will still output zeros (i.e. not float).
- D7 to D0 output-enable is controlled by RWB (CPU read/write signal) being high (read mode) AND'd with the OR'd result of all of the latch enable signals. I.e. if RWB is high and any one of the latch select signals is also high, then D7 to D0 signals will output to the CPU data bus. If the output-enable is disabled, then the pins go high-Z (float).

Note: The 'out nodes' are there to allow controlling of the output to D7 to D0, but still allow other CPLD logic in the CPLD to read the output of any given latch, even if the latch isn't selected.
[edit - minor typos & corrections]

[TomS_]

My experience is that if it works in WinSIM it'll work once programmed into the device.

You might consider changing to an internal address decoder rather than individual register select inputs to save some IOs.

But I've moved on from WinCUPL and now use Altera Quartus to write Verilog instead. You just target and equivalent Altera part and use pof2jed to translate the output to something that is Atmel compatible.

The "compiler" in Quartus does an incredible job of minimising logic usage, sometimes seemingly impossibly. A recent design that I couldn't fit into an ATF1508 when written in CUPL was fit by Quartus in under 100 MCs. It is working some magic under the hood for sure.

[banedon]

Hi TomS_

Thanks for the advice.
I'm not at all familiar with Quartus/Verilog. How do you know which Altera part to target so that you can then convert it? I use Atmel 1504AS and 1508AS CPLDs almost exclusively, with odd ancient Lattice GAL 22v10.
Also, which programmer do you use or do you use a dev board of some description?

[TomS_]

The equivalent Altera parts are

ATF1502AS(V) = EPM7032S
ATF1504AS(V) = EPM7064S
ATF1508AS(V) = EPM7128S

Just choose the same package, they are 1:1 pin compatible. Once you compile your design you need to run the .POF file that Quartus generates through a tool called "pof2jed" which will output a .JED file that you can use to program an Atmel CPLD using ATMISP as normal.

Although it's a little bit more effort, it means I can source any equivalent CPLD for my projects based on availability. Atmel parts all but dried up over the last couple of years but it was possible to find the odd Altera part here and there.

I find Verilog much nicer to write, especially for more complex applications that you would design in a CPLD. CUPL is still fine for simpler stuff using GALs. As an example, I tried implementing a simple text mode VGA controller using WinCUPL and couldn't get it to fit in 128MCs, but Quartus was able to fit the basic design in under 100, and I was able to fit some additional features in the remaining MCs.

https://github.com/tomstorey/vga_crtc

Programmer wise I use a TL866II Plus for GALs, ATDH1150USB for programming Atmel CPLDs via JTAG, and a Terasic USB Blaster "clone" for Altera stuff.

The Atmel programmer came as part of a kit that included a little dev board, but now mostly I just use the programmer directly with parts in my design.

[banedon]

Thanks for that. I've downloaded Quartus and pof2jed - just have to learn how to use it all  .

Equipment wise, I've got:
ATDH1150USB for Atmel CPLDs and Batronix BX48 Batego II for GALs.
I'll take a look at the Terasic USB Blaster, but I'll see if I can wrap my brain around Quartus and Verilog first.

Thanks again for the very useful info  .

[banedon]

Do you need additonal modules for the EPM7128S in Quartus?  I think it's a Max 2, but can't seem to find it. Tried checking all of the other families, but nothing.
Also tried signing into the FPGA part of intel's site and although it seems to accesspt it, when I search for EPM7128S it says I'm not signed in. Tried different browsers. I sthere something that I need to do or active?  In the meantime, I'll keep trying to find a solution.
[edit] Turns out that I needed the earlier version of Quartus II (v.13.01.232). I can now see the MAX7000S devices.

[TomS_]

Yes, sorry, I forgot to mention you need an older version of Quartus since these parts have been EOL for some time now.

It's a very different environment with a bit of a learning curve. ModelSim is used for the simulation side of things, and I would say that had a much bigger learning curve than Quartus itself. I still don't think I've quite figured it out but I can fumble my way through it enough to get some results.

I tend to start by writing and simulating my Verilog in ModelSim, and only later start trying to compile it in Quartus. ModelSim will let you do some things that Quartus won't, so you just have to get used to all of that.

But overall I think it's a nicer development system and produces better results, and certainly has fewer bugs than WinCUPL and WinSim.

[banedon]

Quick question (I'll trya nd make it the last, honest  ): When compiling, I get :

Critical Warning (332012): Synopsys Design Constraints File file not found: 'Test2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

Do you make a point of building such a file, or just trust it'll still optomise ok?

I am compiling a design with latches in it, so this might be the cause of the sdc file not being perhaps autogenerated..?

[c64]

SDC file always need to be created manually

[TomS_]

I dont think I've ever had that before, or I haven't paid attention to it because it has never stopped me from building a design.

The code for the VGA CRTC I linked above compiles just fine, although I don't believe it implements any latches, or at least not knowingly/willingly. Its intent was more or less entirely synchronous (FFs) with some  combinatorial logic.