I believe the point is an extension of the existing Vivado HLS (high-level synthesis) stuff: To suck more software engineers, data scientists, and algorithm designers into FPGA-land, people who may not have any background or interest in hardware design. Xilinx sees this as a major driver of their future growth, primarily because it broadens their user base, but also maybe because it will drive sales of ever-larger FPGAs to accommodate the less efficient designs produced by the new tools!
All of this seems to parallel the trajectory of software. As the dominant stacks become less and less efficient (see: Javascript), they require faster hardware to run effectively. In both worlds (FPGAs and software), engineers with lower-level knowledge will have an edge, as they can do more with less, but only up to a point. For example, we could write all software in C or assembly, but time to market, and maintaining a complex codebase with hundreds of contributors, will often dictate a higher-level paradigm. In ___ years, we may look at hardware design in Verilog/VHDL the way we look at programming a microprocessor in assembly today: crazy efficient, but who has the time?!