Electronics > FPGA

Xilinx coolrunner startup current

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marshallh:
classical CPLDs have a very high power consumption rate, which is linearly proportional to the number of gates.
Newer CPLDs are just stripped down FPGAs and they do have startup inrush, they load bitstream from an onboard eeprom.

Coolrunner II belongs to the former type. If you want to improve power usage consider iCE40.

kubeek:

--- Quote from: marshallh on December 17, 2013, 01:39:34 am ---classical CPLDs have a very high power consumption rate, which is linearly proportional to the number of gates.

--- End quote ---
Do you mean number of gates being flipped at a time, or number of gates on the die regardless of usage? I hope you mean  the first one, since my design is quite slow but needs lots of logic for a FSM, and that is how it looks from the datasheet.

Kohanbash:
It is related to the number of gates used. If you look at the app sheet I posted earlier you can see the equation.

kubeek:
I read the equation beforeand know that this sort of relationship is true for almost all cmos devices, but stil I wanted to make sure of the meaning of that sentence.
Seems the only way to know for sure is to buy the chip and measure both insrush and dynamic current with the firmware loaded.

lorth:

--- Quote from: sdk32285 on December 17, 2013, 01:16:37 am ---The inrush current of a CPLD is typically less than an FPGA (I know there are many different sizes, etc... for each). One key reason for this  is that it is preconfigured (non-volatile) and does not need to be configured at startup like an FPGA (volatile).

--- End quote ---

Careful! as marshallh says, The CoolRunner IS, and should be considered despite Marketing, a Volatile device, since it is SRAM based. There is a non-volatile memory on-chip with the configuration, but the device needs to be programmed at start-up. As you can see in the XAPP388 (page 1):

"Real Digital technology combines a nonvolatile programming cell with a volatile one. Most  digital designers are familiar with shadow memories, where one memory array tracks another one [...]. With Real Digital, the nonvolatile cell is a version of EPROM that is electrically  programmable and the volatile cell is similar to an SRAM cell, but not organized with the same random architecture of an SRAM. [...]"

The only true non-volatile FPGA/CPLD that I know are the ones from MicroSemi, which are Flash based and not SRAM based. (Have you checked the Igloo nano family?)

You might want to check this: http://www.xilinx.com/support/documentation/application_notes/xapp389.pdf

Also, be careful with the power estimators... they do Estimate,... Get a uCurrent Gold (handy the new BW...) and a test the platform...


--- Quote ---Do you mean number of gates being flipped at a time, or number of gates on the die regardless of usage? I hope you mean  the first one, since my design is quite slow but needs lots of logic for a FSM, and that is how it looks from the datasheet.
--- End quote ---
Both, you will have a dynamic and a static power. One does depend on switching frequency, the other we could say it depend with the number of gates.

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