Electronics > FPGA

Xilinx coolrunner startup current

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kubeek:
Hi, I plan to use the coolrunner II CPLD in a very low power system, and I am not sure if the datasheet is not missing the startup current, as other companies state this number (could be beacuse their chips are flash based and the coolrunner seems to be eeprom based, but you never know).
Does anyone use any chip from this family, and could you confirm that the startup current is the same as the running current of the chip?

Kohanbash:
It depends primarily on your clock rate and the number of pins that get set on startup.

Xilinx has power equations for their devices. The part of the inrush current you need to determine is the dynamic portion
http://www.xilinx.com/support/documentation/application_notes/xapp317.pdf

If you use xpower within ISE you can get a more accurate number

kubeek:
Well since the pins / gates that get set are being set only for a tiny fraction of time, shouldn't the startup / inrush current be almost negligible (or high,  but for a tiny amount of time which the supply caps should easily take care of)?

Or at least, the startup current should be less or comparable to the operating current when the chip is running?
I used the xpower from ise, but it states only quiescent and running current. It's the hunderds of miliamps that fpgas devour during configuration that I am worried about. The thing will be powered from a rfid card reader, so my total budget is around 2mA at 1.8V.

nctnico:
There should be some appnotes from Xilinx. Rush-in current used to be a major problem with Xilinx devices but the Coolrunner series was originally developed by Philips (now NXP) so things could be entirely differen. One way to make sure is getting a development board and monitor the current with a scope and a current shunt.

Kohanbash:

--- Quote from: kubeek on December 16, 2013, 09:07:20 pm ---Well since the pins / gates that get set are being set only for a tiny fraction of time, shouldn't the startup / inrush current be almost negligible (or high,  but for a tiny amount of time which the supply caps should easily take care of)?

Or at least, the startup current should be less or comparable to the operating current when the chip is running?
I used the xpower from ise, but it states only quiescent and running current. It's the hunderds of miliamps that fpgas devour during configuration that I am worried about. The thing will be powered from a rfid card reader, so my total budget is around 2mA at 1.8V.

--- End quote ---

I am not positive but yes it should be some small amount for some small amount of time.

The inrush current of a CPLD is typically less than an FPGA (I know there are many different sizes, etc... for each). One key reason for this  is that it is preconfigured (non-volatile) and does not need to be configured at startup like an FPGA (volatile).

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