Is this how MIPI DSI FPGA Bridge implemented? Constructive Criticism needed

[RoadRunner]

I have been using FPGA for small project since quite some time but thoese project were either really simple or made like students. I wanted to increse quality so i have desiced to take relatively complex for the sake of learning. After looking at mike's video on mipi lcd i had decided to implement a spi to spi dsi bridge. Sytem works perferectly can go upto full 60 FPS with MIPI DSI Clock rate of 96Mhz. i have tested with feeding spi from another fpga. I have connected whole fpga setup to PIC32MZ USB HS micro in order to be able to transmit image from PC over USB. In steup with PIC32 SPI @max 50Mhz is limitation.

if any FPGA experts out here will be willing to shine some light on my design will be really helpful.

Project is completely open source. more details can be found here on my blog
https://www.circuitvalley.com/2020/01/spi-mipi-bridge-fpga-verilog-hdl-ipod-nano-nano-lcd-iphone-mipi-lcd.html
Source can be found in my github
https://github.com/circuitvalley/mipi_dsi_bridge_fpga

There is a smally youtube video explaning whole thing, (i am absolute newbie on youtube)

[mon2]

 

@Gaurav yaar, excellent article!! Been reading and reviewing it in details. You should be very proud of this accomplishment.

One thought on how to possibly speed up the USB from host to FPGA transfer is to consider the USB 2.0 HS Cypress FX2LP USB Bridge or perhaps even the more current USB 3.0 USB parallel bridge. Then use LibUSB to xfer the data to the widget.

Have you experimented with more than 1 lane MIPI displays? 2 lane or 4 lane?

Would you know if such multi-lane MIPI displays can be configured to operate with a single lane (at slower display data refresh rates)?

Thanks.