Verilog - elegant solution for variable width definition

[daqq]

Hi guys,

I've got some modules that can be used for varying sample widths. Say you have a 12bit ADC, you instantiate a module with the parameter SampleMSB = 11. The output of the module is a 32bit control register that hooks up to a standard bus the rest of the system shares. The upper 16 bits are used for something else.

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assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:(SampleMSB+1)] = 0;
assign Reg_Out[SampleMSB:0] = SampleOut;Now, this works well, but when I want to use it for 16 bit samples, the code fails, as (SampleMSB+1) is 16 and 15:16 is nonsense.

The obvious way is to keep it unconnected and the compiler will default it to zero, but will issue a warning when the module is used for say, 12 bits.

What would be the elegant way of filling out the rest of the register? I suppose I could use some awful generate command, but I was hoping for something a tad more elegant.

Thanks,

David

[asmi]

I would try something like assign Reg_Out[15:0] = { {(15-SampleMSB){1'b0}}, SampleOut}; just make sure there is a right amount of curly braces (don't have compiler handy to verify syntax). Or even combine the whole 32 bits into a single operator: assign Reg_Out = { SomethingElse, {(15-SampleMSB){1'b0}}, SampleOut}; - this assumes "SomethingElse" is exactly 16 bits.

[SiliconWizard]

Hi guys,

I've got some modules that can be used for varying sample widths. Say you have a 12bit ADC, you instantiate a module with the parameter SampleMSB = 11. The output of the module is a 32bit control register that hooks up to a standard bus the rest of the system shares. The upper 16 bits are used for something else.

Code: [Select]

assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:(SampleMSB+1)] = 0;
assign Reg_Out[SampleMSB:0] = SampleOut;Now, this works well, but when I want to use it for 16 bit samples, the code fails, as (SampleMSB+1) is 16 and 15:16 is nonsense.

The obvious way is to keep it unconnected and the compiler will default it to zero, but will issue a warning when the module is used for say, 12 bits.

What would be the elegant way of filling out the rest of the register? I suppose I could use some awful generate command, but I was hoping for something a tad more elegant.

Note that I don't know much of Verilog - I routinely use VHDL - but wouldn't something like the following work (the equivalent would in VHDL as subsequent assignments just override the earlier ones)?

Code: [Select]

assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:0] = 0;
assign Reg_Out[SampleMSB:0] = SampleOut;

[BrianHG]

Hi guys,

I've got some modules that can be used for varying sample widths. Say you have a 12bit ADC, you instantiate a module with the parameter SampleMSB = 11. The output of the module is a 32bit control register that hooks up to a standard bus the rest of the system shares. The upper 16 bits are used for something else.

Code: [Select]

assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:(SampleMSB+1)] = 0;
assign Reg_Out[SampleMSB:0] = SampleOut;Now, this works well, but when I want to use it for 16 bit samples, the code fails, as (SampleMSB+1) is 16 and 15:16 is nonsense.

The obvious way is to keep it unconnected and the compiler will default it to zero, but will issue a warning when the module is used for say, 12 bits.

What would be the elegant way of filling out the rest of the register? I suppose I could use some awful generate command, but I was hoping for something a tad more elegant.

Thanks,

David

Please verify that this still give you a warning:

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assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:0] = SampleOut[SampleMSB:0];
or this guy (this one is the ''elegant'' one as the " 16'h0' " force defines the unused bits as 0 and the " + " allows the compiler to sum any number of bits from SampleOut, all the way up to 16 bit automatically.):

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assign Reg_Out[31:16] = SomethingElse;
assign Reg_Out[15:0] = 16'h0 + SampleOut[SampleMSB:0];

[daqq]

Thanks everyone, great ideas all around!

Please verify that this still give you a warning:

Will try at work!

[daqq]

So, update:
My original code:

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assign Reg_Out[SampleMSB:0] = MemoryReadData;Generates this kind of warning:

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[Synth 8-3331] design XXX has unconnected port Reg_Out[15]
Other solutions:

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assign Reg_Control_o[15:0] = MemoryReadData[SampleMSB:0];Generates no warning.

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assign Reg_Control_o[15:0] = MemoryReadData;Generates no warning. Will use that.

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assign Reg_Control_o[15:0] = 16'h0 + MemoryReadData[SampleMSB:0];Generates no warning.

Thanks everyone! I was overthinking it


edit: And now to exorcise other warnings that the compiler generates for the input side. The standard control register length is 32 bits as well, but I use only, say, 5 bits of it. As such I get a whole warnings like:

Code: [Select]

[Synth 8-3331] design XXX has unconnected port RegControl_i[12]In the thousands Any reasonable way to fix it on the input side?