Xilinx: interface microblaze to hard IP

[uncleBo]

Hi Everybody! I am a total beginner with FPGA and here is my problem:
I designed an SoC in hardware, something like this: UART->parser->decoder->FIFO->MY_IP
MY_IP is taking data from FIFO and doing something until run_en is ON and FIFO is drained
  Port (
  clk : in std_logic;
  run_en : in std_logic := '0';   -- asynchronous start
  data : in std_logic_vector (39 downto 0);  -- FIFO data
  data_empty : in STD_LOGIC;                   -- FIFO empty
  next_data : out STD_LOGIC := '0';           -- FIFO pop
...
   );

Now I want to migrate to soft definition of UART->[Microblaze: parser->decoder]->
So online video taught me how to start with Microblaze - it reads from UART etc.

Question what would be the proper implementation of interface between Microblaze and MY_IP ? Do I need AXI based FIFO ? Any advice/example of where to start ! Thanks.

[asmi]

I would implement an AXI4-Lite slave interface with a "virtual" register such that the write to it would push that data item into a FIFO. The rest of your system would stay the same - unless you also want to control start/stop of your IP with a Microblaze as well - in that case you will need to implement another register which would start/stop your IP.

One problem is that Microblaze is going to work with 32 bit values, while your data items are 40 bits long, in this case you will need to either implement a pair of "virtual" data registers and rely on MCU following certain protocol (say write MSW first, then write LSW, which would trigger adding the whole thing into a FIFO), or do both writes into the same "virtual" register.

When I talk about "virtual" register, I mean that CPU performs access to a specific address, this access isn't actually stored in a physical register, but instead causes some kind of side effect (like writing into a FIFO).

[uncleBo]

Thanks, asmi! I am following the discussion about AXI4 peripheral programming. Looks like the Xilinx sample code has some issues (https://zipcpu.com/formal/2019/05/13/axifull.html).

[ejeffrey]

Do note that asmi suggested using AXI4-Lite not AXI4.  This is much simpler to get correct and many of the problems demonstrated on that page do not apply to AXI4-Lite. 

That said, it is still tricky to get AXI4-Lite correct, and the zipcpu author also found bugs in the demo AXI4-Lite implementations.  This was all from a few years ago, I'm not sure if Xilinx has fixed some of these issues or not.  Most of them only show up under heavy use especially with multiple masters and slaves communicating at the same time.  That doesn't make it OK, but explains why lots of people use the xilinx AXI IPs every day without problems. 

[asmi]

Yeah, AXI4-Lite is quite simple - no bursts, no byte enables, no "narrow" transfers, no exclusive access, no caching support.

[dtodorov]

To interface custom logic I've used some ready-made IPs from the vivado's catalog. They were called something like GPIO (or IO block), can't recall exactly.
It came ready made with the AXI interface, just managed the memory address allocation.

As for the FIFO - that I guess depends on the data rate vs processing power of the microblaze core. If the CPU is much faster than the data rate of your custom block, hardware FIFO may be a bit of an overplay.