Xilinx IP Core with native data in and AXI bus data out

[FlyingDutch]

Hello Forum,

I have written a design wich produce periodically some data. Data has parallel form 28-bit of data. There also is "strobe" signal (active High) which means that data should be transferred. I am searching for Xilinx Vivado IP Core which on one side has just "native" parallel data and on the second side has AXI bus. Ultimately I would like to send this parallel data in burst by 8 packages. i mean I have stored 28-bit X 8 array and when strobe goes high then I want to send this array by AXI bus in burst mode of length 8. AXI data will has width of 32-bit. What Xilinx IP Core best fits with described behavior?

Thanks in advance and Regards

[asmi]

That sounds like a job for AXI DMA - you program it with destination address of receiving buffer, push data into the AXI Stream port (which is as close as it gets to parallel interface, the only additional signals are two handshake signals - ready/valid, and a "last" signal which indicates an end of the data packet), and then your CPU waits for DMA interrupt signalling completion of transter. Take a look at PG021 to see how it works and how to use it.