Electronics > FPGA

Xilinx ISE -- Coregen DDR Controller IP problem -- Spartan 3e

(1/1)

Harrkev:
OK.  This is driving me NUTS!  I am having problem with the DDR controller generator on Xilinx ISE.

I have the bog-standard Digilent Spartan-3E starter board with a Micron MT46V32M16 (8 Meg x 16 x 4 banks).  I am having trouble with the data lines.

Making a brand-new DDR Controller, I specify an 8-bit address width (keep in mind this part has 16 data lines).  I keep churning through and keeping the default options.  When I get to "Bank Selection" it wants to use 14 data lines!!!

Now, if I go back and choose a 16-bit data width, it wants to use 24 data lines!

Any idea what is going on here?

**EDIT**
According to the Digilent manual for the board, their example UCF file actually fits the entire DRAM IO on bank 3.  For some reason, even if I feed that same UCF file in for guidance, the coregen chokes and dies.

 Note that if I do not select the "right" bank selection, the generator will actually error out without telling me WHY it generated errors, and this is even WITH everything being green on the "Bank Selection" windows.  Any comments?

Thanks in advance.

Scrts:
Did you set up a number of columns and rows in your memory?

Harrkev:

--- Quote from: Scrts on January 20, 2015, 08:30:43 am ---Did you set up a number of columns and rows in your memory?

--- End quote ---
Well, DesignWare knew about the part number (not the speed grade, so I chose one that was slower).

I can choose either 8, 16, or 24 bits for the data width.  For a single DRAM chip, 16 should work perfectly.  Digilent managed to get all pins driven from bank 3 (I assume that they tested it and that it worked).  I, however, cannot convince DesignWare to make a 16-bit interface with just bank 3 without having it die.

Scrts:
Maybe there's a reference design for your board?

David Spicer:
Ththere is a ref design but it dissappeared on new years day. I know because i was using it. You might find it by searching the avnet site. They keep an archive. I think its called design resource centre. Avnet/drc or something like that. Look for obsolete designs/xilinx etc.

The design i am using uses the mpmc ( multi port memory controller) which you can modify in EDK
You only have to put the part number in and it works the rest out. No need

Using old xilinx boards can be a nightmare. I suspect  it's intentional. An insurmountable obstacle tends to arise with licenses or deprecated pcores. I understand where they are coming from. After all, you aren't going to make anything in volume using ddr and a spartan 3e. But that won't make you feel better of course.

Navigation

[0] Message Index

There was an error while thanking
Thanking...
Go to full version