Author Topic: Xilinx ISE - how to improve erratic timing optimization?  (Read 8743 times)

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Offline asmi

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #50 on: July 02, 2020, 02:23:28 pm »
Nah just hobby projects. The only commercial project I've been involved with so far that used an FPGA used a cheap spartan 6 (XC6SLX9).
Well we're discussing real commercial products here. The calculus changes quite a bit when you start shipping your stuff to the customers and you are required to provide support in case something happens in the field.
For commercial prototypes the price of chips is not important as it's still peanuts in R&D budget, and majority of it goes towards paying for engineers' time. When you have to pay 600$ or more per day to every single engineer employed in the project, even 500$+ chips are little more than a pocket change in the grand scheme of things.
« Last Edit: July 02, 2020, 02:49:07 pm by asmi »
 

Online ebastlerTopic starter

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #51 on: July 02, 2020, 02:46:06 pm »
Well we're discussing real commercial products here.

Oops, I didn't realize that.
Pure amateur here. May I stay around?  ::)
 

Offline asmi

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #52 on: July 02, 2020, 02:53:06 pm »
Oops, I didn't realize that.
Pure amateur here. May I stay around?  ::)
Of course you can. Just keep in mind that nobody should ever buy Xilinx chips from the likes of DK for production. If you talk to Xilinx directly, you can get much better prices even if your volume is not very high.

Offline Bassman59

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #53 on: July 02, 2020, 05:55:53 pm »
Oops, I didn't realize that.
Pure amateur here. May I stay around?  ::)
Of course you can. Just keep in mind that nobody should ever buy Xilinx chips from the likes of DK for production. If you talk to Xilinx directly, you can get much better prices even if your volume is not very high.

Uhhh, we (day job) buy Xilinx chips from DigiKey for production. Why? Because we aren't buying the chips by the pallet-load. Xilinx doesn't want to deal with us.

And the price of the chips is a pittance compared to the price of the products. In fact, we "standardize" on two variants of the Artix-7 (and before that, S6) and use them even if they are very oversized for the design, simply to get the price breaks for quantity purchases. And that quantity still isn't enough for Xilinx to care.
 

Offline asmi

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #54 on: July 02, 2020, 06:06:51 pm »
Uhhh, we (day job) buy Xilinx chips from DigiKey for production. Why? Because we aren't buying the chips by the pallet-load. Xilinx doesn't want to deal with us.

And the price of the chips is a pittance compared to the price of the products. In fact, we "standardize" on two variants of the Artix-7 (and before that, S6) and use them even if they are very oversized for the design, simply to get the price breaks for quantity purchases. And that quantity still isn't enough for Xilinx to care.
Why not? Single pallet is only 90 chips. If even that is way too much, then it's not really that kind of production that I was talking about. I'd say it's closer to one-offs, and low volume always have higher overhead.
« Last Edit: July 02, 2020, 06:10:10 pm by asmi »
 

Offline Bassman59

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #55 on: July 02, 2020, 07:18:20 pm »
Uhhh, we (day job) buy Xilinx chips from DigiKey for production. Why? Because we aren't buying the chips by the pallet-load. Xilinx doesn't want to deal with us.

And the price of the chips is a pittance compared to the price of the products. In fact, we "standardize" on two variants of the Artix-7 (and before that, S6) and use them even if they are very oversized for the design, simply to get the price breaks for quantity purchases. And that quantity still isn't enough for Xilinx to care.
Why not? Single pallet is only 90 chips. If even that is way too much, then it's not really that kind of production that I was talking about. I'd say it's closer to one-offs, and low volume always have higher overhead.
Your definition of pallet differs from mine. So when I say "pallet," I mean "Lots of stuff loaded onto a pallet so the pile is about five feet high, and the whole deal is strapped down, and a forklift is used to load the deal onto the truck." 

A pallet is not 90 chips. We call that a "tray." Which we buy.

Yes, your production greatly differs from ours. And my point, which you missed, was that you used the phrase "nobody should ever buy Xilinx chips from the likes of DK for production," without specifying quantity of production. That we do small-scale production of specialist products doesn't mean we don't do production.
 

Offline asmi

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #56 on: July 02, 2020, 07:44:05 pm »
Your definition of pallet differs from mine. So when I say "pallet," I mean "Lots of stuff loaded onto a pallet so the pile is about five feet high, and the whole deal is strapped down, and a forklift is used to load the deal onto the truck." 

A pallet is not 90 chips. We call that a "tray." Which we buy.
Right. I meant to say "tray". I was told you can buy a single tray directly from Xilinx, though haven't tried it yet, but planning to do so in the near future.

Yes, your production greatly differs from ours. And my point, which you missed, was that you used the phrase "nobody should ever buy Xilinx chips from the likes of DK for production," without specifying quantity of production. That we do small-scale production of specialist products doesn't mean we don't do production.
I'm doing the same thing right now, but I don't really consider it "production" in a sense it's not "mass production". Of course it still is production in a project sense (meaning the boards actually go to customers), I should've been more precise with terminology. I'm sorry for confusion.

Offline Bassman59

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #57 on: July 02, 2020, 07:45:33 pm »
Your definition of pallet differs from mine. So when I say "pallet," I mean "Lots of stuff loaded onto a pallet so the pile is about five feet high, and the whole deal is strapped down, and a forklift is used to load the deal onto the truck." 

A pallet is not 90 chips. We call that a "tray." Which we buy.
Right. I meant to say "tray". I was told you can buy a single tray directly from Xilinx, though haven't tried it yet, but planning to do so in the near future.

Yes, your production greatly differs from ours. And my point, which you missed, was that you used the phrase "nobody should ever buy Xilinx chips from the likes of DK for production," without specifying quantity of production. That we do small-scale production of specialist products doesn't mean we don't do production.
I'm doing the same thing right now, but I don't really consider it "production" in a sense it's not "mass production". Of course it still is production in a project sense (meaning the boards actually go to customers), I should've been more precise with terminology. I'm sorry for confusion.

Apology accepted. Even from a Verilog fan.
 

Offline asmi

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Re: Xilinx ISE - how to improve erratic timing optimization?
« Reply #58 on: July 02, 2020, 07:52:51 pm »
Even from a Verilog fan.
You confuse me with someone else. I'm not a Verilog fan.


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