Author Topic: Xilinx ISE implementation stage issues  (Read 375 times)

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Offline promach

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Xilinx ISE implementation stage issues
« on: June 19, 2021, 03:20:03 pm »
Could anyone help with the series buffer and multiple drivers issues ?

 

Offline hamster_nz

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Re: Xilinx ISE implementation stage issues
« Reply #1 on: June 20, 2021, 12:49:00 am »
Possibly could, but could you post text and code rather than a link to an Instagram image? It's unusable on a phone...
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline promach

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Re: Xilinx ISE implementation stage issues
« Reply #2 on: June 20, 2021, 01:21:45 am »
Did you not click the two github links instead of the picture ?
 

Offline hamster_nz

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Re: Xilinx ISE implementation stage issues
« Reply #3 on: June 20, 2021, 02:34:03 am »
Did you not click the two github links instead of the picture ?

Nope, if I couldn't read the image to find out what is wrong why would I bother to go hunting without what is the most likely the most pertinent info?     :-//
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 
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Offline promach

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Re: Xilinx ISE implementation stage issues
« Reply #4 on: June 20, 2021, 04:16:39 am »
user_desired_extra_read_or_write_cycles is not differential signal, why does the tool complain about IBUFDS ?
 



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