Electronics > FPGA
Xilinx ISE implementation stage issues
promach:
Could anyone help with the series buffer and multiple drivers issues ?
hamster_nz:
Possibly could, but could you post text and code rather than a link to an Instagram image? It's unusable on a phone...
promach:
Did you not click the two github links instead of the picture ?
hamster_nz:
--- Quote from: promach on June 20, 2021, 01:21:45 am ---Did you not click the two github links instead of the picture ?
--- End quote ---
Nope, if I couldn't read the image to find out what is wrong why would I bother to go hunting without what is the most likely the most pertinent info? :-//
promach:
user_desired_extra_read_or_write_cycles is not differential signal, why does the tool complain about IBUFDS ?
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