Xilinx MPSoC and RFSoC, what is the big deal?

[matrixofdynamism]

Xilinx invented the Zynq device which combined an ARM core with programmable logic. This was more than 15 years ago I believe.

More recently they released MPSoC and RFSoC FPGAs. From what I know these are massive FPGAs and contained multi-core ARM processors. Now the question in my mind is, what is the big deal? What makes these MPSoC and RFSoC devices special or distinct? We have had ARM core with programmable logic for more than a decade in the market and from different suppliers as well.

[Herby]

As far as I can tell, you've answered your own question already. They're more modern versions of the Zynq. They're bigger, faster and more expensive, but there's nothing fundamentally new.

Small incremental improvements is all you get with mature products (with very rare exceptions). That's true for processors, mobile phones, airplanes, ...

[ejeffrey]

The big deal with the RFSoC was including a ton of high speed data converters on the same chip.  This makes it extremely attractive for custom data acquisition devices, high performance SDR, and similar applications. 

The MPSoC is basically just a bigger zynq.  It has a multi core 64 bit arm CPU, and it also has a dedicated cortex-R processor for realtime and fault tolerant applications.  But the people I know who use them don't really care about those features, the main thing is the much bigger and higher performance programmable logic with many more and faster high speed transceivers.  For instance some versions of the MPSoC can support 4 100 gigabit Ethernet ports.  It's also got more bram, UltraRAM (high density psuedo dual port memory) and more DSP resources.

[glenenglish]

Ultrascale+ parts like MPSoC are revolutionary, compared to 7 series Zynq.

With Ultrascale+, you can utilize, (depending on the design) right up to 99% before they slow down. Compare to 7 series that slow down at > ~  70% (design dependent). They are awesome.

and the fabric is fast --even in the slowest parts, 650 MHz+  multipliers....

The dual core R5 can run lockstep and is in its  own power domain.  The R5 is not  just another ARM cortex M, it is a processor that can unwind itself out of trouble, out of aborts,  sorts out instructions half executed etc, it is design to keep on trucking

With all this comes a great deal of complexity. beware of this !  You could learn every about MPSoC and it might take you a lifetime.
You can spend a year reading the datasheets thoroughly. And, you want a simple watchdog ? then you better get to know and write custom firmware for the PMU !

But Altera 10nm  Agilex 5 with  HPS ( in midrange 50k-300k) will  go head to head  and beyond later this year  in production....  Unless you need to go to market now, I think Agilex5 is worth waiting for.

RFSoC is fantastic, but IMO is only useful when you need half a dozen 5GHz converters, and  their dynamic performance is not particularly good at < 500 MHz compared to say, a $35   12 bit 250 MHz converter,  but they are not designed to compete in that region. they compete in the 1-10 GHz large instantaneous BW  region.

7 series ZYNQ still holds the market sweetspot below then 50k LE region though, and small 225 and 400 0.8mm ball packages

Other notable SoC options are Microchip Polarfire SoC , Efinix Titanium SoC,  . Forget Cyclone IV SOC.. ROFL.

[matrixofdynamism]

Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.

So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.

[asmi]

Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.

So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.

Easy - PL is to perform the primary function of a device, and PS is to run the HMI (GUI, peripherals, etc.). A lot of devices require APU to run the HMI in addition to the main FPGA which does the processing. Combining these into the single chip has a lot of advantages - smaller PCBs, less power consumption, easier routing, etc. If only these MPSoCs wouldn't cost so much, they would be a no-brainer for a lot of applications.

[KE5FX]

You tend to see the SoCs used in MIMO applications like cellular base station transceivers, or in high-end radar work where cost is no object.  For everything else, it is usually going to be cheaper to hook your own choice of ADCs and DACs up to your own choice of FPGA and controller hardware.

At least that's been the case historically. 

[radar_macgyver]

RFSoC's big advantage relative to a big FPGA coupled to high speed converters is that the interface between the two (in the latter case) is non-trivial. Even with standardization like JESD204B, it's really hard to get right even when using someone else's known working boards. Integrating the converters on chip means you have direct access to the parallel data stream without a complex SERDES in between. The drawback is that the converters can have noise coupling in from the digital part of the SoC. They are also really expensive.

[ejeffrey]

An RFSoC in volume direct from Xilinx is actually competitive with stand alone FPGA + high speed data converters.  And for low volumes, the eval boards are not exactly cheap (~$15k), but are a real bargain considering what you get and what it would cost to get an equivalent.

In addition, the interconnect bandwidth is higher.  Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited.  Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.

Of course in addition to possible noise, a limitation of the RFSoC is that you only get the configurations xilinx makes.  If it's overkill for your needs you don't get a discount, while if it's not sufficient it won't work.

[radar_macgyver]

An additional concern with JESD204 is that if you change the sample rate (or interpolation/decimation config for converters that support it), one must go through a lengthy retraining and re-syncing sequence. With the older (external) parallel converters, this was not usually a concern. I haven't worked with an RFSOC yet (too expensive!) but I imagine it will be similar in this regard.
To be fair, most applications such as cell base-stations or radar transceivers don't require frequent sample rate changes. Oscilloscope digitizers would need this ability, though.

In addition, the interconnect bandwidth is higher.  Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited.  Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.

There are some rather impressive parts like the ADC08DJ5200RF that can do 10.4 GSPS without internal decimation, but require eight JESD204 lanes at 17 Gbps for a single channel. The newer RFSOCs now include hard-IP digital downconverters. Most communications/radio applications for such devices would use a DUC/DDC anyway so it's not much of a loss.

[glenenglish]

I have worked with RFSoC parts. Fantastic for specific jobs. If you are worried about cost, then you are trying to use it in the wrong market.

IMO, they're only cost effective compared to multiple 5Gsps converters, and the spurs in the passb relegate it to wideband  functions, as the SFDR isnt really all that great for any high dynamic range narrowband application, and the sampling clocks are polluted.

There's another aspect for their use - and that is link power consumption
as radar_macgyver says, high speed external DCs , they chew up JESD lanes like nothing else. That has a power cost and silicon area cost to get between the DC and the FPGA. extra pain avoided by one package.

For the ADC side - If used as a back end   , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications  (wideband, lots if computation) and cellular phone base stations. Both are relatively low dynamic range applications. 

When the fabric multipliers run at 650 MHz and you are filtering a signal (say a wideband correlator ) at 5 Gsps, you chew up multipliers and rams big time....  A 100 tap non symmetrical fir is going to chew 1000 multipliers ! LOL.

[radar_macgyver]

For the ADC side - If used as a back end   , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications  (wideband, lots if computation) and cellular phone base stations. Both are relatively low dynamic range applications. 

(emphasis mine)
Spot on - my usual radar applications are the opposite (relatively narrow-band, very high dynamic range). I'm curious what the applications of wideband radar are, if you're allowed to share (the only one that comes to mind is ground-penetrating radar). For narrowband (or indeed, multiple narrowband channels, typical of basestation applications), an off-chip converter with integrated DDCs would be significantly lower cost. Power consumption increase due to the JESD204 lanes and their associated transceivers will likely be offset by the thousands of DSP blocks!

[matrixofdynamism]

FPGAs are themself not ubiquitous like ARM based cores or other microprocessor, microcontroller and DSPs. However, it seems that even within the FPGA domain, the RFSoC and MPSoC are for niche applications. The demand must be high enough that Xilinx went ahead and created such devices.

What I have understood is that the integrated data converters are a huge plus. But what about the multicore ARM processors of different types that exist? How would I harness them?

Also, I believe that some other companies (Maybe Microchip) have come with this idea to have a small amount of programmable logic in their microcontrollers. Has anyone used these type of tools at all?