Xilinx SDK - preconfigure DDR with data?

[JohnnyMalaria]

Hello,

I'm developing a Zynq-based FPGA project that ultimately will receive data from 4 ADC channels. As part of testing, I want to use simulated data that are generated from a separate application on a PC. I can successfully use the Xilinx SDK's Dump/Restore Data File option to load the contents of a local binary file (0.25MB) to a specified location of the Zynq's DDR. That involves creating the necessary space on the heap with malloc and determining its address. i.e., I have to run my C application in debug mode so I can break execution immediately after creating the array and use Dump/Restore to load the binary file. This is tedious and prevents me from running my test app as a release configuration.

Is there a way to have the linker process preconfigure a region of DDR memory with the contents of a file that I can then access from my C app?

Thanks.

[BrianHG]

Which HDL are you using.  Usually in SystemVerilog test bench, I would just:

bin_src = $fopen("bin_file_name.bin","rb"); // open "bin_file_name.bin" for read binary.

and make a loop with:

while (! $feof(bin_src)) {
          adc_input_port = $fgetc(bin_src);
          // either toggle the ADC clock input, or wait for the FPGA to clock the ADC...//
         // monitor results...
}

You can use the same technique to fill any ram inside the FPGA or for DDR ram, it depends on the DDR memories model's capabilities which may already have a dedicated source power-up file like what's available in Mircron's DDR3 model.

In fact, I would usually generate the test data inside the test-bench file instead of loading data.
Also, the data may also be in ASCII table format if you want to decode such things...

[JohnnyMalaria]

Which HDL are you using.  Usually in SystemVerilog test bench, I would just:

bin_src = $fopen("bin_file_name.bin","rb"); // open "bin_file_name.bin" for read binary.

and make a loop with:

while (! $feof(bin_src)) {
          adc_input_port = $fgetc(bin_src);
          // either toggle the ADC clock input, or wait for the FPGA to clock the ADC...//
         // monitor results...
}

You can use the same technique to fill any ram inside the FPGA or for DDR ram, it depends on the DDR memories model's capabilities which may already have a dedicated source power-up file like what's available in Mircron's DDR3 model.

In fact, I would usually generate the test data inside the test-bench file instead of loading data.
Also, the data may also be in ASCII table format if you want to decode such things...

I'm running a standalone application on the Zynq ARM, so there's no file system.

Unfortunately, I can't create the test data from the test bench. It's generated by a pretty complicated Monte Carlo simulation that is written in Python and runs on a desktop PC. I did try generating a C include file from the Python program to create the data array but the it's too large for the compiler.

[JohnnyMalaria]

I found a way Not sure if it's safe but it works. See attached screenshot.

[BrianHG]

Ooops, sorry.  My code was designed to take your python sim data binary file and feed it to the ADC input pins on the FPGA as if it were sample data coming in from an actual connected ADC, ie run the project as if it were a real world scenario.  It was not intended to stuff/force/initialize it's way into the simulation Zynq ARM's ram.

asmi probably knows the best way to do this.

[asmi]

It was not intended to stuff/force/initialize it's way into the simulation Zynq ARM's ram.

He is talking about running it on a real hardware, not simulation.

asmi probably knows the best way to do this.

Unfortunately, I don't. I've never worked with Zynqs as I prefer working with pure FPGAs.