Xilinx SliceM LUTs as distributed RAMs: read-first, write-first, or selectable?

[SMB784]

I know that for Xilinx parts, block RAM ports can be specified as read-first or write-first when accessing a shared read/write port.  I cant find any information on whether or not the Xilinx SliceM LUT RAMs share this capability with their block RAM cousins.  Does anyone know?

[langwadt]

the LUT RAM is async read, I seems to remember an app note describing it as similar to write first on a block RAM

[SMB784]

Yeah I read that it's got asynchronus read (with the option for synchronus read if you implement a flipflop on the read port).  I am wondering if it is possible to configure these rams as READ FIRST.

[langwadt]

https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Read-First-mode-in-7-Series-Distributed-Rams/td-p/669251

[SMB784]

https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Read-First-mode-in-7-Series-Distributed-Rams/td-p/669251

Perfect, thank you! Very helpful!

[NorthGuy]

With distributed RAM, you simply write to the configuration bits of the LUTs.