Entry level FPGA engineer interviw questions feedback.

[Dmeads]

Hi all,

I compiled a bunch of FPGA interview questions from reddit and youtube. The following document is my best answers in the moment with no google searching (just brain use haha). I would love some feedback if you have the chance.

number 16 asks to create a simple state machine. I used verilog because It is what i am most familiar with. It took me about 25 min to write and simulate the RTL and the testbench with comments. I could probaly do it in 18 if i wasnt tired

Code: [Select]


// Can you code a simple state machine?


// I will use Verilog.


`timescale 1ns / 1ps

module SM(
input clk,
input [1:0] some_input,
output [1:0] some_output
);


reg [1:0] STATE;           // state of machine
reg [1:0] output_0 = 2'b00;              // various outputs
reg [1:0] output_1 = 2'b01;
reg [1:0] output_2 = 2'b10;

reg [1:0] r_some_output = 0;         // register to hold output (assign later)

localparam STATE_0 = 0;    // states
localparam STATE_1 = 1;
localparam STATE_2 = 2;

always @ (posedge clk)
begin
case(STATE)

STATE_0 : begin

if (some_input == 0)
begin
r_some_output <= output_0;  // change outputs
STATE <= STATE_1;           // change state
end
else      // else remain in same state
STATE <= STATE_0;
end // STATE_0


STATE_1 : begin

if (some_input == 1)
begin
r_some_output <= output_1;  // change outputs
STATE <= STATE_2;           // change state
end
else
STATE <= STATE_1;
end // STATE_1


STATE_2 : begin

if (some_input == 2)
begin
r_some_output <= output_2;  // change outputs but stay in state 2
end
else
STATE <= STATE_2;
end // STATE_2


default : begin

STATE <= STATE_0;

end // default

endcase // case(STATE)
end // always block

assign some_output = r_some_output;

endmodule

////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module tb;
reg clk;
reg [1:0] some_input;
wire [1:0] some_output;

always #5 clk = ~clk;      // create clock signal

SM uut(clk,some_input,some_output);

initial
begin
$dumpfile("test.vcd");
$dumpvars(0,uut);

clk = 0;
some_input = 2'b00;  // move through various inputs to change states.
#20
some_input = 2'b01;
#20
some_input = 2'b11;
#20
$finish;
end //initial
endmodule




[hamster_nz]

> 8 ). What is Metastability, what is it caused by, and how do you avoid it (in a FPGA)?

Answer is very vague... I like the answer to 14 much better. The answer needs to have "asynchronous input" in it somewhere, and "setup/hold time violation" in it. Clock domain crossing don't 'cause' it, it is just where it can happen. A good clock domain crossing design solves metastability issues..

> 10). What is the difference between a Melee and a Moore machine

You need to work in this one. It is one of those concepts that "egg heads" like to push. In practice it is academic - a bit like "behavioral" vs "structural" designs.

> 12) Name some latches.

I don't that "NAND", "NOR" are are latch types.

[SiliconWizard]

For Moore/Mealy, you can read this, which is short and to the point: https://en.wikipedia.org/wiki/Mealy_machine

Many people writing HDL code these days don't really care about how to call their FSMs, but those will usually fall within one category or the other.

[Dmeads]

Thanks sounds like I got some things to to work on