Electronics > FPGA

Zynq Based Digital Camera Design Help (issues with Zynq)

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Boscoe:
Hi all,

I'm currently undertaking a project very dear to me - a digital camera. For some reason it's become a real desire of mine to design, make and use a digital camera of my own that's actually good! I've designed and made the first revision of electronics, testing it and starting on the software. I'm having some small issues with the hardware and would like to ask for some advice here. Once I have the first revision done I'm going to actively push the project into the world to encourage others to contribute to the project in whatever direction they would like to take it.

You can read a little behind the project and a blog of it's first revision development here in a google doc.

https://docs.google.com/document/d/1gnEBzrgK05kzuTFEPspbsJ127sbl_kKvJMLyx1T--wY/

You can download the repo, schematics and gerevers etc. here:

https://github.com/gswdh/CameraElectronics/releases

I'd be very keen to hear people's general opinions etc. on the project!

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The issue:
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There's an MCU (referred to as the PMC, power management controller) on the PCB that just controls the power. The camera is charged by USB C and the PMC deals with this and setting up the charging of the battery as well as power sequencing the rest of the PCB's supply rails.

I have successfully powered the board, programmed the PMC and sequenced the rest of the PCB without any power issues.

The Zynq is accessible over the JTAG but only the PL part, not the PS (arm-dap) in the default configuration of the electronics.

I'm using a 50Mhz input clock on the PS as the 33.3MHz variant wasn't in stock at the time of ordering.

I'm able to fix not seeing the arm-dap in the JTAG chain by chaining the Zynq's boot mode to PLL bypass.

Now I have made a simple UART print project that doesn't use the DDR3 for the Zynq and built the code project successfully in Vitis with the PS input clock frequency set to 50MHz. I have set all the items to be stored in ps7_ram_0 rather than the ps7_ddr_0 region in the linker script.

When I go to debug the project on the HW the process get's stuck at the ps7_init stage. I believe this is because the PLL never locks as it's bypassed but it's difficult to get any real information here.

There's a few forum posts on AMD's (Xilinx's) website regarding hanging on the ps7_init stage but the only solutions are to disable the PLL bypass (which doesn't work for me) or add some lines to the ps7_init.tcl to disable waiting for the PLLs to lock.



My question is:

Why would I need to enable PLL bypass in order to get the arm-dap to show in the JTAG chain? Could it be a design issue or could it be because I'm not using a 33.3MHz clock? I'm struggling to work that one out.



Many thanks!!!

Boscoe:
So I have made progress and got a program running. I had to edit the ps7_init.tcl to adapt for the fact the PLL is bypassed. I'm still none the wiser on why it won't show in the JTAG chain with the PLL enabled tho. I find the Xilinx docs extremely difficult to find - the Zynq 7000 only has the timing datasheet so finding any info on the required frequency for the PS clock has so far been fruitless.

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