Zynq Ultrascale+ RFSoC data converter port help

[knight]

Hello. Can anyone help me understand the port functions of the RF data converter IP? I tried reading the product guide but it is badly written in my opinion.
 
I have attached the IP block and the settings configuration. So, the adc_clock is 2GHz and AXI_stream_clock is 250MHz. What exactly is axi_stream_clock? Is it the frequency at which FPGA fabric will communicate with RF-ADC? If not, then what is the FPGA frequency required.

Need help with understanding these ports: sysref_in, s_axi_clk, m0_axis_aclk, clk_adc0 and irq.

Link to product guide: https://docs.xilinx.com/r/en-US/pg269-rf-data-converter
Thanks.

[Mario87]

Reference clock is just that...an external clock used as a reference, what speed is the oscillator on your board?

axi_stream_clock is the clock speed of the data stream within the FPGA fabric itself.

sysref_in - not checked the product guide, so not sure, but try clicking on the + to expand and see what is there, it might give you a clue.

s_axi_clk - slave AXI clock, this is the clock at which the blocks within your FPGA fabric will operate at to communicate to one another and send basic information back and forth (like commands to adjust operational modes from the CPU), this in particular is a slave input and would connect to a master of some other device (CPU for example).

m0_axis_aclk - Master AXI Stream Clock, this is the clock speed of your actual data stream within your FPGA fabric, like for example with HD video this might be 148.5MHz, but your AXI clk for comms between modules might be something different

clk_adc0 - This looks like the clk speed of your ADC?? Not checked the manual, but I would say a pretty safe guess

irq - Interrupt Request